models/*: (1/3) optimize positon calc core

* Removed FIFO before each Divider Core. Now, we are using
  a simple upsampling + pulse stretcher

* Using 8 Clock per division in all Divider Cores

* Increase transition bandwidth of TBT filter. Decrease number
  of coefficients from more than 800 to around 240

* Using 3 CIC sections instead of 5 for FOFB and Monit.
  rates

* Changed from Parellel CORDIC to a complete Serial

* Using Embedded Multiplier for Compensation in CORDIC

* Using Mults in all Kx, Ky and Ksums

* Fix wrong cast in FOFB rate
hdl/modules/*/generated/virtex6/*: (2/3) optimize positon calc core

* Removed FIFO before each Divider Core. Now, we are using
 a simple upsampling + pulse stretcher

* Using 8 Clock per division in all Divider Cores

* Increase transition bandwidth of TBT filter

* Decrease number of coefficients from more than 800 to
  around 240.

* Using 3 CIC sections instead of 5 for all rates

* Changed from Parellel CORDIC to a complete Serial

* Using Embedded  Multiplier for Compensation In CORDIC

* Using Mults in all Kx, Ky and Ksums

* Fix wrong cast in FOFB rate
hdl/modules/*/generated/artix7/*: (3/3) optimize positon calc core

* Removed FIFO before each Divider Core. Now, we are using
 a simple upsampling + pulse stretcher

* Using 8 Clock per division in all Divider Cores

* Increase transition bandwidth of TBT filter.

* Decrease number of coefficients from more than 800 to
  around 240.

* Using 3 CIC sections instead of 5 for all rates

* Changed from Parellel CORDIC to a complete Serial

* Using Embedded  Multiplier for Compensation In CORDIC

* Using Mults in all Kx, Ky and Ksums

* Fix wrong cast in FOFB rate