Single DFG execution is scheduled and three control bits are added to words in the outside-addr-buffer
Minibenchmark: Add DFG generation of matrix multiplication when inner most loop is partially unrolled
Rewrite the DFG generation to make sure the DFG interface compatible.
Update all the benchmark to generate IR(DFG etc.) for FPGA acceleration
Modify the scheduler to use the newest IR generated by the new benchmark
Add script that coucompletes the DFG generation, scheduling and bitstream integration