defconfig
msm: camera: Fix CCI I2C write fail to write for reg addr 0x00 Allow CCI I2C write to 0x00 addressed register in data queue.

Change-Id: I6f3844c95fd6e6d258326e410826da0ee3c27bda
Signed-off-by: Lokesh Kumar Aakulu <lkumar@codeaurora.org>
Signed-off-by: klozz <xxx.reptar.rawrr.xxx@gmail.com>
msm:isp: avoid race condition in stop axi stream during axi stop stream, axi halt and reset hw may run in parallel and can cause list corruption.

Change-Id: I5da1fa8a4a5d6a273cb7a818fba0db6027159795
Signed-off-by: Alok Kediya <kediya@codeaurora.org>

(MODIFIED)
Signed-off-by: klozz <xxx.reptar.rawrr.xxx@gmail.com>
camera: isp: create debug fs entry to log vfe overflows Added entry in fs to log occurence of overflow from vfe

CRs-Fixed: 661343

Change-Id: Id398d11aaa84fca4ea63ea523c78c564c7eb6999
Signed-off-by: Katta Santhisindhu <kattas@codeaurora.org>
Signed-off-by: klozz <xxx.reptar.rawrr.xxx@gmail.com>
msm:camera: Bus overflow recovery mechanism Add bus overflow recovery mechanism in the isp driver. When the bus overflow happens we will halt the bus, reset the isp and burst count and restart the stream.

Change-Id: I7a1a4e1c28e346036405db4ce9a2362109bd4f95
Signed-off-by: Abhishek Kondaveeti <akondave@codeaurora.org>
Signed-off-by: klozz <xxx.reptar.rawrr.xxx@gmail.com>
msm: isp: Fix stats mask upon VFE reset. When streamoff is issued, a HARD reset is done for VFE. This causes the stats register to be reset to zero. It needs to be properly initialized with the last used mask upon init.

Change-Id: I5e2fcab0358e63272f40458862f4cf6a7d3bb4bc
Signed-off-by: Abhishek Kondaveeti <akondave@codeaurora.org>
Signed-off-by: klozz <xxx.reptar.rawrr.xxx@gmail.com>
msm-camera: move target checks to userspace move all the target specific checks to userspace.

Change-Id: I67f3aec92a0cc0bba1a239958c200c54834a349a
Signed-off-by: Alok Kediya <kediya@codeaurora.org>
Signed-off-by: klozz <xxx.reptar.rawrr.xxx@gmail.com>
V2 msm:isp: avoid race condition in stop axi stream during axi stop stream, axi halt and reset hw may run in parallel and can cause list corruption.

Change-Id: I5da1fa8a4a5d6a273cb7a818fba0db6027159795
Signed-off-by: Alok Kediya <kediya@codeaurora.org>
Signed-off-by: klozz <xxx.reptar.rawrr.xxx@gmail.com>
Fix typo + USB: gadget: qdss: Fix strncmp length usage Using a newer GCC we get the following warnings:

drivers/usb/gadget/f_qdss.c: In function 'qdss_bind_config':
drivers/usb/gadget/f_qdss.c:598: warning: argument to 'sizeof' in
'strncmp' call is the same expression as the second source; did you mean
to provide an explicit length? [-Wsizeof-pointer-memaccess]

drivers/usb/gadget/f_qdss.c: In function 'usb_qdss_open':
drivers/usb/gadget/f_qdss.c:760: warning: argument to 'sizeof' in
'strncmp' call is the same expression as the second source; did you mean
to provide an explicit length? [-Wsizeof-pointer-memaccess]

These look to be due to using sizeof(ch->name) which is a pointer, use
a simple strcmp instead.

Change-Id: I09e09a18ffb3361fc351b177ed3a35432d9ed933
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: klozz <xxx.reptar.rawrr.xxx@gmail.com>
ARM: gic: use a private mapping for CPU target interfaces

The GIC interface numbering does not necessarily follow the logical
CPU numbering, especially for complex topologies such as multi-cluster
systems.

Fortunately we can easily probe the GIC to create a mapping as the
Interrupt Processor Targets Registers for the first 32 interrupts are
read-only, and each field returns a value that always corresponds to
the processor reading the register.

Initially all mappings target all CPUs in case an IPI is required to
boot secondary CPUs.  It is refined as those CPUs discover what their
actual mapping is.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Blechd0se <alex.christ@hotmail.de>
ARM: 7660/1: tlb: add branch predictor maintenance operations

The ARM architecture requires explicit branch predictor maintenance
when updating an instruction stream for a given virtual address. In
reality, this isn't so much of a burden because the branch predictor
is flushed during the cache maintenance required to make the new
instructions visible to the I-side of the processor.

However, there are still some cases where explicit flushing is required,
so add a local_bp_flush_all operation to deal with this.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Blechd0se <alex.christ@hotmail.de>
ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead

Many ARMv7 cores have hardware page table walkers that can read the L1
cache. This is discoverable from the ID_MMFR3 register, although this
can be expensive to access from the low-level set_pte functions and is a
pain to cache, particularly with multi-cluster systems.

A useful observation is that the multi-processing extensions for ARMv7
require coherent table walks, meaning that we can make use of ALT_SMP
patching in proc-v7-* to patch away the cache flush safely for these
cores.

Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Blechd0se <alex.christ@hotmail.de>
ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2

commit bf3f0f332f76a85ff3a0b393aaded5a8533769c0 upstream.

Commit ae8a8b9553bd ("ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE
and use ALT_SMP instead") added early function returns for page table
cache flushing operations on ARMv7 SMP CPUs.

Unfortunately, when targetting Thumb-2, these `mov pc, lr' sequences
assemble to 2 bytes which can lead to corruption of the instruction
stream after code patching.

This patch fixes the alternates to use wide (32-bit) instructions for
Thumb-2, therefore ensuring that the patching code works correctly.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Blechd0se <alex.christ@hotmail.de>