spi: zynq-qspi: Use readl_/writel_relaxed functions instead of readl/writel

Since the qspi register space configured as device memory and the order of
accesses arriving at Device memory is guaranteed to correspond to the program
order of instructions which access Strongly-ordered or Device memory.
The readl/writel function contains a barrier and adding more delay while
accessing the data from the fifo registers

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynq-qspi: Use autostart mode and avoid fifo status checks

For better throughput, always use manual chipselect and autostart mode and also
avoid fifo status check while accessing the fifo.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynq-qspi: Avoid temp variables used in fifo read/write operations

For better throughput, Avoid temporary variable for storing the fifo data and
copying to user buffer and vice versa, Instead of that use the buffer directly

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynq-qspi: Improve the transfer rate

The following sequence is used to keep spi bus busy and transfer rate
1. Configure the Rx threshold register with optimum value
2. Fill the complete Tx fifo
3. Wait for the Rx fifo not empty or Tx fifo empty condition
4. Read data from the Rx fifo for Rx threshold entries or requested
   no of bytes if the outstanding bytes are less than the threshold
5. Fill the Tx fifo with Rx threshold entries or requested no of
   bytes if the outstanding bytes are less than the threshold
6. Repeat step 2

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>