radeonsi: Don't modify PA_SC_RASTER_CONFIG register value if rb_mask == 0

E.g. this could happen on older kernels which don't support the
RADEON_INFO_SI_BACKEND_ENABLED_MASK query yet. The code in
si_write_harvested_raster_configs() doesn't deal with this correctly and
would probably mangle the value badly.

Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
egl: Fix non-dri SCons builds re #87657

* Revert change to egl main producing Shared Libraries
* Check for dri before including dri code
vc4: Fix the argument type for cl_u16().

It doesn't matter, since it just got truncated to 16 inside, anyway.
vc4: Don't bother zero-initializing the shader reloc indices.

They should all be set to real values by the time they're read, and
ideally if you used valgrind you'd see uninitialized value uses.
vc4: Handle unaligned accesses in CL emits.

As of 229bf4475ff0a5dbeb9bc95250f7a40a983c2e28 we started getting SIBGUS
from unaligned accesses on the hardware, for reasons I haven't figured
out.  However, we should be avoiding unaligned accesses anyway, and our CL
setup certainly would have produced them.