corrected PHY pin 16: AVDDH, not AVDDL
removed rs232 sheet
changed schematic net label sizes for readability
connect PHYAD2 through 10k resistors to allow strapping without interfering with clock function
footprint library table
converted all 10k resistors to 0603
converted daisho.mod to .pretty
changed switcher caps to 0805
PCB layer legend
changed to correct QSH footprint, removed PHYAD2 connections (pull-downs are good enough)
corrected ISET resistor value
permanently pulled up V2P5_EN for FPGA I/O supply startup
updated date on silkscreen