cc2538: Add adc driver and example

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
cc2538: Support any UART baudrate.
Fix rounding error in baudrate calculation.
Change uart_set_baudrate() to a do-while statement.
Eliminate UART_CONF_IBRD and UART_CONF_FBRD.
The UDP socket API code
The TCP socket API code
Fix CPU clock calibration in msp430f2xxx based platforms (e.g. Zolertia Z1).

The following problems were present in the existing DCO calibration algorithm:

Problem #1. In function msp430_quick_synch_dco(), the "for(i=0; i < 1000; i++) { .. }" loop is optimized away by the compiler, as i is not volatile. Making i volatile would improve the results, but would not be sufficient: see the next point.

Problem #2. According to MSP430F2617 Device Erratasheet, bug BCL12 precludes a naive implementations of "fast" calibration altogether. The bug is present on all MCU revisions up to date.

The description of the bug:
"After switching RSELx bits (located in register BCSCTL1) from a value of >13 to a value of <12 OR from a value of <12 to a value of >13, the resulting clock delivered by the DCO can stop before the new clock frequency is applied. This dead time is approximately 20 us. In some instances, the DCO may completely stop, requiring a power cycle.

Furthermore, if all of the RSELx bits in the BSCTL1 register are set, modifying the DCOCTL register to change the DCOx or the MODx bits could also result in DCO dead time or DCO hang up."

In Contiki code for msp430f2xxx @ 8MHz, the RSEL search currently typically goes from 15 down to 11, thus violating the rules.

Step-by-step RSEL change is proposed as the best possible workaround:
"[..] more reliable method can be implemented by changing the RSEL bits step by step in order to guarantee safe function without any dead time of the DCO."

Problem #3. The old Contiki code started from the highest possible calibration values: RSEL=15, DCOx=7. According to MSP430F2617
datasheet, this means that the DCO frequency is set to 26 MHz. For one, Vcc under 3V is not supported for this frequency, so this means that battery-powered nodes have a big problem. The minimal operating voltages are:
- 1.8V for RSEL <= 13
- 2.2V for RSEL = 14
- 3.0V for RSEL = 15
So the correct way is to always start calibration from RSEL <= 13, unless explicityly pre-calibred values are present.

Problem #4. Timer B should be turned off after the calibration, following the "Principles for Low-Power Applications" in MSP430 user's Guide.

The patch fixes these issues by performing step-by-step calibration and turning off Timer B afterwards. As opposed to MSP430F1xxx calibration, this algorithm does not change the ACLK divider beforehand; attempts to make calibration more precise would lead to looping in some cases, as the calibration step granularity at larger frequencies is quite big.

Additionally, the patch improves DCOSYNCH_CONF_ENABLED behavior, allowing the resynchronization to correct for more than one step.
Use the same scale for ETX calculation as for rank calculations to avoid conversion errors between the two.
The check should be whether RPL_DIS_SEND is non-zero, not whether it is defined.
Avoid calling rpl_lock_parent for uninitialized memory. Renamed p to parent to make reading easier.
Ensure that the objective function's reset function is called at least once. This will enable the objective function to initialize itself during run-time.
Cleaned up some of the comments and output strings.
Merge pull request #608 from nvt/rpl-fixes

Minor RPL improvements
Makefile.include: Setting RELSTR based on git tags requires to be in
the contiki directory
Merge pull request #606 from atiselsts/master

Fix MCU clock calibration in msp430f2xxx based platforms (e.g. Zolertia Z1)
TCP socket server example
Add a compile test for the tcp-socket example
Include udp-socket.h and tcp-socket.h by default in all applications that include contiki-net.h
Merge pull request #620 from adamdunkels/push/socket-api

New TCP and UDP socket APIs