cfgrs: set Architeture Version Reg to 1.1-rev0
cappuccino/fetch: prevent burst signal on regular bus accesses

The ic_refill signal can go high slightly before a regular bus
access have finished.
The burst signal out to the bus interface has to be held off
until the regular bus access is done.
Merge branch 'master' of git://github.com/openrisc/mor1kx into multicore
cappuccino: check atomic_reserve at end of storebuffer

Since there might be a snooped access while the atomic store
(l.swa) is in the storebuffer, the atomic_reserve flag has to
be checked right when the l.swa is coming out from the
store buffer and let out on the bus.

This achieves this by stalling the pipeline while the
l.swa is in the store buffer.

There are a couple of reasons why the atomic goes through
the store buffer and not bypass it.
1) It simplifies some of the logic (less special cases)
2) The store buffer should have knowledge about atomic stores
   going through it, since it place restrictions on what kind
   of re-ordering can be done.
   The current simple store buffer does no such things,
   but this way we are a little more future-proof.