[sma_corr] Laura has implemented 50% duty cycle reads from the DDR3.

This means that at fast FPGA clock rates the 10 GbE transmit code should
keep up with our instantaneous visibility data rate without over flowing
the TX buffer.

This also required a minor change to the visibs packetizer logic.
[sma_corr] Integration time should now update on the next accumulation.

This was done by registering the internal integration time and hooking up
the new_acc signal to the enable.
[sma_corr] Added a default to the integration time register (and also a software read-out).
[sma_corr] Replaced the hard-coded 11 in Dave's network block with vectors_per_wstep.

The xeng_sync signal should now have the correct period at any Walsh-commenserate
sample/FPGA rate.