power: qpnp-bms: disable interrupts at probe

The ocv and cc threshold interrupt are required when the battery is
FULL. Disable them at probe time and enable them once the battery is
reported full.

Change-Id: I75bc0b9128f7a8552380ba184d8a72e54159c01d
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
power: qpnp-bms: use consistent IAVG for raw SOC calculation

Currently the BMS uses the instantaneous current for the raw SOC
calculation. However, this current can be very high because of the boot
tiime power draw. This can bias the UUC to unreasonably levels (100% of
the battery when at cold temperatures) and cause the saved shutdown SOC
to be needlessly discarded.

Use the more realistic IAVG of 250 mA when doing this initial raw SOC
calculation as well in other places where iavg is being reset to avoid
skewing the results. Also, do not save the percent UUC when doing the raw
SOC calculation. Rather, use the loaded shutdown IAVG if there is one.

Change-Id: I426b824a50568b01bae442a3154e7c68c42409f8
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
power: qpnp-bms: always release output locks in bms driver

If a SPMI read error occurs, there can be a situation where the
BMS_HOLD_OREG bit is not set and the bms param lock is never released.
This can cause deadlocks and battery SoC to never move. Fix this by
releasing the locks after handling an error.

Change-Id: I880b8e1ed2ff1ec3ce701f1e9922c9aac353766a
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
power: qpnp-bms: fix coulomb counter selection

There is a bug in the BMS code right now where reading the coulomb
counter actually reads the shadow coulomb counter and vice versa. Fix
this by correctly specifying the coulomb counter to be read.

Change-Id: Ica703d1e426e595e9ff6cd9fc45bade743740238
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
power: qpnp-bms: do not adjust when shutdown soc is being applied

When the shutdown SOC is being applied, do not adjust the SOC before
using it for reporting. This is to prevent situations where the SOC can
be adjusted upwards when discharging, or adjusted downwards when
charging, but before the monotonic filtering can apply.

This change will ensure SoC monotonicity during discharge across power
cycles.

Change-Id: I23c95ddb941e0544920eb5c4cac3b1ba8d2752d6
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
msm: socinfo: Introduce soc string

OEMs require the soc-id to be translated to a string
by the kernel and reported as a part of machine init
routines. Add support for it

Change-Id: I1ebdcd21061bde60815090a2d7de475a4e235f0a
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Mao Jinlong <c_jmao@codeaurora.org>
power: qpnp-bms: clamp for SOC <= 0

In some scenarios a negative soc may be calculated even
though VBAT is above the cutoff voltage.

The clamping function does not take negative SOC values
into account and fails to clamp the SOC. Fix this
by checking for SOC values <= 0.

CRs-Fixed: 623091
Change-Id: I8d64b3c8717e8088be71d84d66225512b85e87e3
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
(cherry picked from commit 1ed4fee365c0d4b07d1644e864222fffda13da58)
regulator: mem-acc-regulator: Add a driver to control the MEM ACC

The memory accelerator (MEM ACC) controls the delays applied during
memory access. These delays vary based on the power-mode (corner)
on which the memory is connected. This driver adds a regulator
interface to configure the power-mode of the memory accelerator
based on the APC (application processor) corner.

CRs-fixed: 638439
Change-Id: I830ff000f8a16c4d3de5bdebf48d424354ddb086
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Signed-off-by: Ke Liu <keliu@codeaurora.org>
msm: Camera: Return proper value for msm_camera_qup_i2c_txdata().

msm_camera_qup_i2c_txdata() is not returning proper value.
Due to which session tear down is not happening properly
in case of i2c failure.
CRs-Fixed: 640328

Change-Id: Iac8be9d4755f807b45a6ede4f660b52cb88aedd4
Signed-off-by: Vivek Veenam <vveenam@codeaurora.org>
mdss: Add newline to VSYNC timestamp for mdp3 driver

This makes sure that the userspace correctly interprets the end
of the vsync timestamp.

CRs-Fixed: 639039
Change-Id: I8a0810283a42a9c39a3c8fe36b862bbfd3ecdbea
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
mdss: mdp3: Remove extra call to clk_prepare

clk_prepare got moved inside mdp3_clk_update. Prior to this patch
unprepare would never be called successfully.

Change-Id: I28ab035b42d433f379d63748ac4f506a8575ea66
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
ARM: dts: msm: Increase the drive strength for MSM8610v2

At lower 10mA random CRC errors are seen. With 12mA drive
strength for clock lines the issue is not seen

CRs-Fixed: 601882
Change-Id: If2b3246c78a2d73acdedb76da964badb0e133bdd
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
msm: camera: Fix race condition between camera driver and camera daemon

Delete checking command list before calling
wait_for_competion_timeout which could cause race condtion
if camera daemon may respond fast and there is one context swtich
between msm_enqueue and completion.

Change-Id: I28bdc4e344d2365acf49d422ba75dc64308a96aa
Signed-off-by: Yiduo Wang <yiduow@codeaurora.org>
msm: camera: Fix improper memory free in failure case

Remove improper drv_priv free in failure case and
add NULL pointer check to avoid kernel panic

Change-Id: If074eba245e93bf8fead505993a2611582e4398d
Signed-off-by: Yiduo Wang <yiduow@codeaurora.org>
platform: qpnp-power-on: Set boot reason in procfs

Assigns a value to the boot_reason procfs property in
qpnp-power-on. This property can be read via
/proc/sys/kernel/boot_reason. The value for this property
will reflect lowest bit set in the PON_REASON1 PMIC register.
For example, if bit 0 is set in the register, then
boot_reason will have a value of 1. If no bits are set
in the register, then boot_reason will have a value of 0.

For existing PMIC chips, the following mapping applies
for the value of boot_reason:

0 -> unknown
1 -> hard reset
2 -> sudden momentary power loss (SMPL)
3 -> real time clock (RTC)
4 -> DC charger inserted
5 -> USB charger inserted
6 -> PON1 pin toggled (for secondary PMICs)
7 -> CBLPWR_N pin toggled (for external power supply)
8 -> KPDPWR_N pin toggled (power key pressed)

Change-Id: Icf2be66165fd01d3063282fcbfb2b115480e7b5c
Signed-off-by: Maria Yu <aiquny@codeaurora.org>
Merge "msm: mdss: error handling in the dsi driver on 8x10"
Merge "msm: mdss: abstract the dsi command utility API"
Merge "msm: mdss: use the common dsi utility api"
Merge "msm: mdss: use the dsi panel API for sending init commands"
Merge "msm: mdss: update the dsi interrupt handling on 8x10"