Changed PC_match output to use a delay_line

Used to experiment with manual retiming. No improvement. Left at depth 0.
Enabled ROUTER_CLOCKING_TOPOLOGY_ANALYSIS to add beneficial clock skew

Generally fixes the wraddr to lutram critical paths when using MLABs.
No CAD time impact. Improves Fmax by 2-3%.
Crit paths afterwards without common cause across seeds, so likely as good as they can get.
Parameterized Addressing memories depths.

Enables easy experiments with shallower/deeper Addressing memories.
Adjusts memory map address alignments to follow.
Still many hardcoded values here, so will need work later.