UPSTREAM: mwifiex: abort scan while cancelling pending command

mwifiex_cancel_pending_ioctl() and
mwifiex_cancel_all_pending_cmd() are called in command timeout
and driver unload paths respectively.
If scan operation is in progress, we should abort it smoothly.

Reported-by: Tim Shepard <shep@alum.mit.edu>
Signed-off-by: Amitkumar Karwar <akarwar@marvell.com>
Signed-off-by: Bing Zhao <bzhao@marvell.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

BUG=chrome-os-partner:26626
TEST=run "./reload_network_device.sh mlan0; sleep 30" in a loop
for 50 times.

Change-Id: Ied436f3efd612ebf7186e614d6f935f7cf8e2eb3
Reviewed-on: https://chromium-review.googlesource.com/190169
Reviewed-by: Paul Stewart <pstew@chromium.org>
Tested-by: Bing Zhao <bzhao@marvell.com>
Commit-Queue: Bing Zhao <bzhao@marvell.com>
UPSTREAM: mwifiex: clean pcie ring only when device is present

Write io memory to clean PCIe buffer only when PCIe device is
present else this results into crash because of invalid memory
access.

Cc: <stable@vger.kernel.org>
Signed-off-by: Avinash Patil <patila@marvell.com>
Signed-off-by: Bing Zhao <bzhao@marvell.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

BUG=chrome-os-partner:26626
TEST=run "./reload_network_device.sh mlan0; sleep 30" in a loop
for 50 times.

Change-Id: I60e21dd51620d57b81770bd4bd681995e602dd0a
Reviewed-on: https://chromium-review.googlesource.com/190180
Reviewed-by: Paul Stewart <pstew@chromium.org>
Tested-by: Bing Zhao <bzhao@marvell.com>
Commit-Queue: Bing Zhao <bzhao@marvell.com>
UPSTREAM: mwifiex: add NULL check for PCIe Rx skb

We may get a NULL pointer here if skb allocation for Rx packet
was failed earlier.

Cc: <stable@vger.kernel.org>
Signed-off-by: Amitkumar Karwar <akarwar@marvell.com>
Signed-off-by: Bing Zhao <bzhao@marvell.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

BUG=chrome-os-partner:24397
TEST=Issue 24397 c#96 captured a skb allocation failure which
caused kernel crash. I'm not able to reproduce it but this CL
should fix the crash in theory.

Change-Id: I624f48917aa613a9abc1c9c17c59e99fccccde38
Reviewed-on: https://chromium-review.googlesource.com/190181
Reviewed-by: Paul Stewart <pstew@chromium.org>
Tested-by: Bing Zhao <bzhao@marvell.com>
Commit-Queue: Bing Zhao <bzhao@marvell.com>
ARM: Speed up page list initialization during boot

During boot, we populate the page lists by using the page freeing
mechanism on every individual page.  Unfortunately, this is very
inefficient because the memory manager spends a lot of time coalescing
pairs of adjacent free pages into bigger blocks.

Rather than adding a single page at a time, we can take advantage of the
fact that we know that all the pages are available and free up big
blocks of pages at a time instead.

BUG=chrome-os-partner:26945
TEST=platform_BootPerf, seconds_power_on_to_kernel

Change-Id: Ifaad5df1bc310e5e675a332cff8cdad5b3011055
Signed-off-by: Chirantan Ekbote <chirantan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190381
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
CHROMIUM: video: tegra: sor: Do not attach again if attached

We have a check in sor attach function to see if the SOR is already
attached with dc. But we removed it in commit:

b7fe34b02322 CHROMIUM: video: tegra: Fix SOR attach sequence

This makes sometime(50%) the display doesn't come up on some boards.

So this patch adds the check back.

BUG=None
TEST=nyan & nyan big display is OK(tested 5 times on each board)
     LP0 stress test didn't find SOR timeouts(5 times, each ~200 cycles)

Change-Id: Ifacd456f20ccdf5efe072ef3307dbb8e0480fd18
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/190448
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: video: tegra: host: gk20a: Check for free va fail

Return error if freeing virtual address space fails. Do not try to
free graphics context that has not been allocated.

BUG=None
TEST=System boots OK

Change-Id: I6d1dd23bc4a5819768bd2d4186c04bec78bd32b8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/190449
Tested-by: Mark Zhang <markz@nvidia.com>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: DPTF kernel driver update to 8.0.9

Added support for UI tuning overrides.

Added primitive to set depth limit for P/T states and
	RAPL power limit.

Modified handling for suspend/resume events for S3.

Minor code clean-up and incremented the version to 8.0.9.

BUG=chrome-os-partner:25110
TEST=Manually tested
CQ-DEPEND=CL:190335

Change-Id: I60851d4021e43ffab8bdb01b7bc385d95ff3b41f
Signed-off-by: Brad Geltz <brad.geltz@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/190334
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
UPSTREAM: usb: class: cdc-acm: be careful with bInterval

bInterval must be on the range 1 - 16, if we
want to pass the maximum allowed, we should
be passing 16

Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

BUG=chromium:345086
TEST=Tested the following:
     - USE="-kernel_next kernel-3_10" ./build_packages
     - Manually tested cellular support on a DUT with alt3100 and y3300 modems
     - On the same devices, ran network_3GIdentifiers, network_3GModemPresent,
       network_3GSmokeTest

(cherry picked from commit d102e78f7035f2d6896ced598122b878afd1c352)
Signed-off-by: Prathmesh Prabhu <pprabhu@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187331
Reviewed-by: Ben Chan <benchan@chromium.org>
Change-Id: Iae431cdb6026b2a19e4ad61f7a2a6d4327ac57b0
Reviewed-on: https://chromium-review.googlesource.com/190402
CHROMIUM: ARM: dts: tegra124: remove 204Mhz for SDIO

Running SDIO at 204 Mhz on T124 is causing CRC errors.
Disable it for now.

BUG=None
TEST=wifi speedtest

Change-Id: I097384bc7a4d35b94e4406e4d81447e593681235
Signed-off-by: Christopher Freeman <cfreeman@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/188213
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: nyan: Improve HDMI signal integrity

Update the HDMI power and voltage settings on nyan.
These settings improves the eye diagram signal.

BUG=none
TEST=HDMI eye diagram tests passes on Big.

Change-Id: Iafe509e236fb3b69fdf9c4e9e0fce86fa2f0e4d8
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/189690
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: ARM: dts: nyan: add Big EMC tables

Add EMC tables for Big with Ram code = 1.

BUG=none
TEST=Built kernel and boot.

Change-Id: I0ef413c5d210ba27b32d8e5c5ca10a87f5549ee7
Signed-off-by: Danny Huang <dahuang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/189945
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
BACKPORT: ASoC: Intel: Fix corruption in BYT PCM driver.

The PCM ops in BYT PCM driver are over writing the RTD driver data causing
corruption after first playback or capture has been opened. Fix this by not
using snd_soc_pcm_set_drvdata(). There are no other users of
snd_soc_pcm_set_drvdata upstream so this needs to be removed uptream too.

BUG=chrome-os-partner:26908
TEST=apply full patch set. Run aplay and arecord simulteneously, see
no kernel crash.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
(cherry picked from commit 7b5497d6193416b15e81ecae1bb1a5c6f90a50dc)

Change-Id: I595f795ec128e4b0b185cfcbfb9a56332f01a8c3
Signed-off-by: Hsin-Yu Chao <hychao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190462
Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Benson Leung <bleung@chromium.org>
Tested-by: Benson Leung <bleung@chromium.org>
CHROMIUM: ASoC: Intel: Use stream direction to access pcm_data

Originally the private data of sst-baytrail driver keeps
two copy of pcm_data and letting streams access it using the
id of cpu_dai.  This causes a problem when doing capture and
playback to the same device simultaneously, since these two
streams are sharing the same pcm_data.

Change to use stream direction as index to access the two
pcm_data, so that we can open two streams of different
direction on the same device concurrently.

BUG=chrome-os-partner:26908
TEST=Manual: Run aplay and arecord concurrently on rambi.
See no kernel crash.

Change-Id: I084434faa165e440d8106d50e7533ff4e0b31ae8
Signed-off-by: Hsin-Yu Chao <hychao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190297
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Benson Leung <bleung@chromium.org>
Tested-by: Benson Leung <bleung@chromium.org>
CHROMIUM: config: enable bridging options

Shouldn't add any real overhead as these are all modules.

BUG=chromium:348809
TEST=`emerge-amd64-generic chromeos-kernel-next` enables new bridge options as modules

Change-Id: I8f761986a09355eb3675805f2dc5a9bccc28b4bf
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190058
Reviewed-by: Olof Johansson <olofj@chromium.org>
BACKPORT: drm/i915: add bunit read/write routines

For modifying self-refresh exit latency.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

http://cgit.freedesktop.org/~danvet/drm-intel/log/?h=drm-intel-next
(cherry picked from commit f34191585ff30849ab80a03c2bb4294db4cfbffc)

BUG=None
TEST=System boots with a 3200x1800 EDP display attached, open terminal
and use xrandr to verify display resolution.

Change-Id: Ic46152c53de858138562ef4c24949320c1d76ffb
Signed-off-by: Brian J Lovin <brian.j.lovin@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/183976
Reviewed-by: Dominik Behr <dbehr@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
BACKPORT: drm/i915: move VLV DDR freq fetch into init_clock_gating

We don't want it delayed with the RPS work.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

http://cgit.freedesktop.org/~danvet/drm-intel/log/?h=drm-intel-next
(cherry picked from commit 85b1d7b3f475c6425707b2e064f9c0f54058019d)

BUG=None
TEST=System boots with a 3200x1800 EDP display attached, open terminal
and use xrandr to verify display resolution.

Change-Id: If633628242c97e7c7acd18d4f3dec425c56ac975
Signed-off-by: Brian J Lovin <brian.j.lovin@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/183977
Reviewed-by: Dominik Behr <dbehr@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
CHROMIUM: sdhci: platform callback for voltage switch

Allow sdhci platform driver to do some processing after
voltage switching takes place.

BUG=chrome-os-partner:26969
TEST=Boot and file copy on SD card

Signed-off-by: Christopher Fremean <cfreeman@nvidia.com>

Change-Id: I23d7f9f122eb05ed7a6c55b57f928bba9e083dd6
Reviewed-on: https://chromium-review.googlesource.com/190425
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: sdhci: tegra: calibrate after voltage switch

Tegra sdhci controller must run autocalibration after
voltage switching.

BUG=chrome-os-partner:26969
TEST=Boot and file copy on SD card

Change-Id: I0c6445eacba0171e237d7b46e1ad3e939a5f1f9a
Signed-off-by: Christopher Freeman <cfreeman@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/190441
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: ARM: dts: nyan: fix sdmmc3 regulator

The regulator for sdmmc3 is for the signal voltage (vqmmc)

BUG=chrome-os-partner:26969
TEST=Boot via SD card

Signed-off-by: Christopher Freeman <cfreeman@nvidia.com>

Change-Id: Ic1eb4a49ded9d011ecf291d1eac109dabbea8458
Reviewed-on: https://chromium-review.googlesource.com/190426
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: sdhci: tegra: allow external loopback to be disabled

Per the tap hole tuning algorithm for T124, we need to disable
the external loopback on the SD card slot.  This provides a
device tree property for that.

BUG=chrome-os-partner:26969
TEST=Boot via UHS SD card

Change-Id: Ia54d79a10bd4115b287ba96cc4dc27525d10ab13
Signed-off-by: Christopher Freeman <cfreeman@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190428