sim_core: fix rcall instruction cycles...

Based on the instrtiming.elf code and checking the Avr Instruction
 Manual, RCALL was found to be producing incorrect cycle counts.

Atmega; 3, 16-bit pc; 4, 22-bit pc.

Fixed accordingly.

	modified:   sim/sim_core.c
Merge pull request #68 from bsekisser/master-core-fix-rcall-cycles

sim_core: fix rcall instruction cycles...
sim_core: flag equations refactored.

Most flag equations have been refactored into flag group function
  blocks...  The core passes all provided tests in the tests folder
  and now most especially is able to pass the instruction test code.
  At the same time, the overall average cycles per instruction has
  ticked down.

	modified:   sim/sim_core.c