[mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rather than 16-bit in MIPS32r6/MIPS64r6

Summary:
The error message for the invalid.s cases isn't very helpful. It happens because
there is an instruction with a wider immediate that would have matched if the
NotMips32r6 predicate were true. I have some WIP to improve the message but it
affects most error messages for removed/re-encoded instructions on
MIPS32r6/MIPS64r6 and should therefore be a separate commit.

Depens on D4115

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4117

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211012 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Merge most of the big/little endian checks in atomic.ll

Summary:
There is very little difference between the big and little endian cases in
test/CodeGen/Mips/atomic.ll. Merge them together using multiple
FileCheck prefixes.

Depends on D4117

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4118

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211013 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64] Fix a fencepost error in lowering for llvm.aarch64.neon.uqshl.

Patch by Jiangning Liu!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211014 91177308-0d34-0410-b5e6-96231b3b80d8