updated ini with the new queue lengths for the read and writes queues at the ctrl and ftl levels
updated the ini files to contain the new logging options related to the new plane, ftl and ctrl queue logs
added logging fix so that NVDIMM log is saved when running with NVDIMM
stupid ini differences forced a commit
removed preprocessor NVDIMM check since hybridsim won't ever run without NVDIMM
Merge branch 'master' of https://github.com/jimstevens2001/HybridSim
moved the call to NVDIMM save stats outside of the HybridSim enable logs if block
Added C interface for Python frontend.

The C interface enables users of HybridSim to create instances of
HybridSim using Python's ctypes.cdll interface.  The only complication
here is that cdll cannot handle callbacks, so this interface requires
the user to poll.  A commit in the near future will provide a Python
class to wrap the C interface.
HybridSim Python Interface

Using the C external interface and Python's ctypes module, the
hybridsim.py file creates a Python wrapper to HybridSim. The main function
of the file shows how to instantiate and use it.  This will be used as
the basis for a Python version of the trace-based simulation and later
for a specialized prefetching simulator.
Port TraceBasedSim.cpp to Python.

Porting TBS over to Python in prep for the Multithreaded TBS.
Minor fix to tbs.py
Initial commit of mt_tbs.py

It is not fully functional yet.
Multithreaded TBS now functional

mt_tbs.py now has the following capabilities:

* Specify trace files, core count, and explicit schedule.
* Use single trace file to create multiple threads.
* Multi-core works fine.
* Detailed output of what happened at the end of the run.

Missing features:
* Different base addresses for threads reusing the same trace file.
* Config file (currently config is hard-coded).
Added scheduler prefetcher infrastructure

The hooks for performing scheduler prefetching are now implemented.
A first version of the page tracking algorithm is also implemented.
Currently, this cannot issue prefetches because HybridSim does not
expose an interface to do so.
Bugfixes/improvements to mt_tbs.py

Bugfix: forced addr in addTransaction to use c_ulonglong(). Previously,
addr was getting cut off at 32-bits for large addresses.

Improvement: Added THREAD_PENDING_MAX to track how many outstanding
accesses are allowed per thread. When the number of outstanding
accesses is at its max, the throttle_cycles is incremented instead of
trace_cycles. This was also necessary to get decent performance for many
cases (otherwise, the HybridSim pending queue would get massive and slow
things down to a halt).
Commiting yaml config file.
Minor fix for type handling in hybridsim.py
Add PREFETCH_RANGE MMIO operation.
Initial very simple implementation of scheduler prefetching.

This algorithm simply prefetches any pages touched the last quantum
a thread executed.
MT-TBS improvements.

* Update the schedule to remove threads that are done and replace them
  with threads that still have work to do.
* Output the done threads list at the end of each quantum.