Add execution + assembler tests of AArch64 TRN Intrinsics.

	* gcc.target/aarch64/simd/vtrnf32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnf32.x: New file.
	* gcc.target/aarch64/simd/vtrnp16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnp16.x: New file.
	* gcc.target/aarch64/simd/vtrnp8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnp8.x: New file.
	* gcc.target/aarch64/simd/vtrnqf32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqf32.x: New file.
	* gcc.target/aarch64/simd/vtrnqp16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqp16.x: New file.
	* gcc.target/aarch64/simd/vtrnqp8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqp8.x: New file.
	* gcc.target/aarch64/simd/vtrnqs16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqs16.x: New file.
	* gcc.target/aarch64/simd/vtrnqs32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqs32.x: New file.
	* gcc.target/aarch64/simd/vtrnqs8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqs8.x: New file.
	* gcc.target/aarch64/simd/vtrnqu16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqu16.x: New file.
	* gcc.target/aarch64/simd/vtrnqu32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqu32.x: New file.
	* gcc.target/aarch64/simd/vtrnqu8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqu8.x: New file.
	* gcc.target/aarch64/simd/vtrns16_1.c: New file.
	* gcc.target/aarch64/simd/vtrns16.x: New file.
	* gcc.target/aarch64/simd/vtrns32_1.c: New file.
	* gcc.target/aarch64/simd/vtrns32.x: New file.
	* gcc.target/aarch64/simd/vtrns8_1.c: New file.
	* gcc.target/aarch64/simd/vtrns8.x: New file.
	* gcc.target/aarch64/simd/vtrnu16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnu16.x: New file.
	* gcc.target/aarch64/simd/vtrnu32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnu32.x: New file.
	* gcc.target/aarch64/simd/vtrnu8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnu8.x: New file.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210148 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-07  Richard Biener  <rguenther@suse.de>

	libcpp/
	* configure.ac: Always set need_64bit_hwint to yes.
	* configure: Regenerated.

	* config.gcc: Always set need_64bit_hwint to yes.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210149 138bc75d-0d04-0410-961f-82ee72b054a4
Really delete gcc/loop-unswitch.c.

	gcc/
	* loop-unswitch.c: Delete.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210150 138bc75d-0d04-0410-961f-82ee72b054a4
Reimplement AArch64 TRN intrinsics with __builtin_shuffle.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/vtrns32.c: Expect zip[12] insn rather than trn[12].
	* gcc.target/aarch64/vtrnu32.c: Likewise.
	* gcc.target/aarch64/vtrnf32.c: Likewise.

gcc/ChangeLog:

	* config/aarch64/arm_neon.h (vtrn1_f32, vtrn1_p8, vtrn1_p16, vtrn1_s8,
	vtrn1_s16, vtrn1_s32, vtrn1_u8, vtrn1_u16, vtrn1_u32, vtrn1q_f32,
	vtrn1q_f64, vtrn1q_p8, vtrn1q_p16, vtrn1q_s8, vtrn1q_s16, vtrn1q_s32,
	vtrn1q_s64, vtrn1q_u8, vtrn1q_u16, vtrn1q_u32, vtrn1q_u64, vtrn2_f32,
	vtrn2_p8, vtrn2_p16, vtrn2_s8, vtrn2_s16, vtrn2_s32, vtrn2_u8,
	vtrn2_u16, vtrn2_u32, vtrn2q_f32, vtrn2q_f64, vtrn2q_p8, vtrn2q_p16,
	vtrn2q_s8, vtrn2q_s16, vtrn2q_s32, vtrn2q_s64, vtrn2q_u8, vtrn2q_u16,
	vtrn2q_u32, vtrn2q_u64): Replace temporary asm with __builtin_shuffle.




git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210151 138bc75d-0d04-0410-961f-82ee72b054a4
Add execution + assembler tests of AArch64 EXT intrinsics.

	gcc.target/aarch64/simd/ext_f32.x: New file.
	gcc.target/aarch64/simd/ext_f32_1.c: New file.
	gcc.target/aarch64/simd/ext_p16.x: New file.
	gcc.target/aarch64/simd/ext_p16_1.c: New file.
	gcc.target/aarch64/simd/ext_p8.x: New file.
	gcc.target/aarch64/simd/ext_p8_1.c: New file.
	gcc.target/aarch64/simd/ext_s16.x: New file.
	gcc.target/aarch64/simd/ext_s16_1.c: New file.
	gcc.target/aarch64/simd/ext_s32.x: New file.
	gcc.target/aarch64/simd/ext_s32_1.c: New file.
	gcc.target/aarch64/simd/ext_s64.x: New file.
	gcc.target/aarch64/simd/ext_s64_1.c: New file.
	gcc.target/aarch64/simd/ext_s8.x: New file.
	gcc.target/aarch64/simd/ext_s8_1.c: New file.
	gcc.target/aarch64/simd/ext_u16.x: New file.
	gcc.target/aarch64/simd/ext_u16_1.c: New file.
	gcc.target/aarch64/simd/ext_u32.x: New file.
	gcc.target/aarch64/simd/ext_u32_1.c: New file.
	gcc.target/aarch64/simd/ext_u64.x: New file.
	gcc.target/aarch64/simd/ext_u64_1.c: New file.
	gcc.target/aarch64/simd/ext_u8.x: New file.
	gcc.target/aarch64/simd/ext_u8_1.c: New file.
	gcc.target/aarch64/simd/ext_f64.c: New file.
	gcc.target/aarch64/simd/extq_f32.x: New file.
	gcc.target/aarch64/simd/extq_f32_1.c: New file.
	gcc.target/aarch64/simd/extq_p16.x: New file.
	gcc.target/aarch64/simd/extq_p16_1.c: New file.
	gcc.target/aarch64/simd/extq_p8.x: New file.
	gcc.target/aarch64/simd/extq_p8_1.c: New file.
	gcc.target/aarch64/simd/extq_s16.x: New file.
	gcc.target/aarch64/simd/extq_s16_1.c: New file.
	gcc.target/aarch64/simd/extq_s32.x: New file.
	gcc.target/aarch64/simd/extq_s32_1.c: New file.
	gcc.target/aarch64/simd/extq_s64.x: New file.
	gcc.target/aarch64/simd/extq_s64_1.c: New file.
	gcc.target/aarch64/simd/extq_s8.x: New file.
	gcc.target/aarch64/simd/extq_s8_1.c: New file.
	gcc.target/aarch64/simd/extq_u16.x: New file.
	gcc.target/aarch64/simd/extq_u16_1.c: New file.
	gcc.target/aarch64/simd/extq_u32.x: New file.
	gcc.target/aarch64/simd/extq_u32_1.c: New file.
	gcc.target/aarch64/simd/extq_u64.x: New file.
	gcc.target/aarch64/simd/extq_u64_1.c: New file.
	gcc.target/aarch64/simd/extq_u8.x: New file.
	gcc.target/aarch64/simd/extq_u8_1.c: New file.
	gcc.target/aarch64/simd/extq_f64.c: New file.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210152 138bc75d-0d04-0410-961f-82ee72b054a4
Add execution + assembler tests of AArch64 REV Neon Intrinsics.

	* gcc.target/aarch64/simd/vrev16p8_1.c: New file.
	* gcc.target/aarch64/simd/vrev16p8.x: New file.
	* gcc.target/aarch64/simd/vrev16qp8_1.c: New file.
	* gcc.target/aarch64/simd/vrev16qp8.x: New file.
	* gcc.target/aarch64/simd/vrev16qs8_1.c: New file.
	* gcc.target/aarch64/simd/vrev16qs8.x: New file.
	* gcc.target/aarch64/simd/vrev16qu8_1.c: New file.
	* gcc.target/aarch64/simd/vrev16qu8.x: New file.
	* gcc.target/aarch64/simd/vrev16s8_1.c: New file.
	* gcc.target/aarch64/simd/vrev16s8.x: New file.
	* gcc.target/aarch64/simd/vrev16u8_1.c: New file.
	* gcc.target/aarch64/simd/vrev16u8.x: New file.
	* gcc.target/aarch64/simd/vrev32p16_1.c: New file.
	* gcc.target/aarch64/simd/vrev32p16.x: New file.
	* gcc.target/aarch64/simd/vrev32p8_1.c: New file.
	* gcc.target/aarch64/simd/vrev32p8.x: New file.
	* gcc.target/aarch64/simd/vrev32qp16_1.c: New file.
	* gcc.target/aarch64/simd/vrev32qp16.x: New file.
	* gcc.target/aarch64/simd/vrev32qp8_1.c: New file.
	* gcc.target/aarch64/simd/vrev32qp8.x: New file.
	* gcc.target/aarch64/simd/vrev32qs16_1.c: New file.
	* gcc.target/aarch64/simd/vrev32qs16.x: New file.
	* gcc.target/aarch64/simd/vrev32qs8_1.c: New file.
	* gcc.target/aarch64/simd/vrev32qs8.x: New file.
	* gcc.target/aarch64/simd/vrev32qu16_1.c: New file.
	* gcc.target/aarch64/simd/vrev32qu16.x: New file.
	* gcc.target/aarch64/simd/vrev32qu8_1.c: New file.
	* gcc.target/aarch64/simd/vrev32qu8.x: New file.
	* gcc.target/aarch64/simd/vrev32s16_1.c: New file.
	* gcc.target/aarch64/simd/vrev32s16.x: New file.
	* gcc.target/aarch64/simd/vrev32s8_1.c: New file.
	* gcc.target/aarch64/simd/vrev32s8.x: New file.
	* gcc.target/aarch64/simd/vrev32u16_1.c: New file.
	* gcc.target/aarch64/simd/vrev32u16.x: New file.
	* gcc.target/aarch64/simd/vrev32u8_1.c: New file.
	* gcc.target/aarch64/simd/vrev32u8.x: New file.
	* gcc.target/aarch64/simd/vrev64f32_1.c: New file.
	* gcc.target/aarch64/simd/vrev64f32.x: New file.
	* gcc.target/aarch64/simd/vrev64p16_1.c: New file.
	* gcc.target/aarch64/simd/vrev64p16.x: New file.
	* gcc.target/aarch64/simd/vrev64p8_1.c: New file.
	* gcc.target/aarch64/simd/vrev64p8.x: New file.
	* gcc.target/aarch64/simd/vrev64qf32_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qf32.x: New file.
	* gcc.target/aarch64/simd/vrev64qp16_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qp16.x: New file.
	* gcc.target/aarch64/simd/vrev64qp8_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qp8.x: New file.
	* gcc.target/aarch64/simd/vrev64qs16_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qs16.x: New file.
	* gcc.target/aarch64/simd/vrev64qs32_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qs32.x: New file.
	* gcc.target/aarch64/simd/vrev64qs8_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qs8.x: New file.
	* gcc.target/aarch64/simd/vrev64qu16_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qu16.x: New file.
	* gcc.target/aarch64/simd/vrev64qu32_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qu32.x: New file.
	* gcc.target/aarch64/simd/vrev64qu8_1.c: New file.
	* gcc.target/aarch64/simd/vrev64qu8.x: New file.
	* gcc.target/aarch64/simd/vrev64s16_1.c: New file.
	* gcc.target/aarch64/simd/vrev64s16.x: New file.
	* gcc.target/aarch64/simd/vrev64s32_1.c: New file.
	* gcc.target/aarch64/simd/vrev64s32.x: New file.
	* gcc.target/aarch64/simd/vrev64s8_1.c: New file.
	* gcc.target/aarch64/simd/vrev64s8.x: New file.
	* gcc.target/aarch64/simd/vrev64u16_1.c: New file.
	* gcc.target/aarch64/simd/vrev64u16.x: New file.
	* gcc.target/aarch64/simd/vrev64u32_1.c: New file.
	* gcc.target/aarch64/simd/vrev64u32.x: New file.
	* gcc.target/aarch64/simd/vrev64u8_1.c: New file.
	* gcc.target/aarch64/simd/vrev64u8.x: New file.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210153 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/
	* tree-vect-data-refs.c (vect_grouped_load_supported): New
	check for loads group of length 3.
	(vect_permute_load_chain): New permutations for loads group of
	length 3.
	* tree-vect-stmts.c (vect_model_load_cost): Change cost
	of vec_perm_shuffle for the new permutations.

gcc/testsuite/
	PR tree-optimization/52252
	* gcc.dg/vect/pr52252-ld.c: Test on loads group of size 3.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210155 138bc75d-0d04-0410-961f-82ee72b054a4
More gcc/loop-unswitch.c cleanup.

	gcc/
	* cfgloop.h (unswitch_loops): Remove.
	* doc/passes.texi: Remove references to loop-unswitch.c
	* timevar.def (TV_LOOP_UNSWITCH): Remove.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210156 138bc75d-0d04-0410-961f-82ee72b054a4
gcc:
        * config/epiphany/epiphany.c (epiphany_handle_interrupt_attribute):
        Emit an error when the function has arguments.
gcc/testsuite:
        * gcc.target/epiphany/isr-arg.c: New file.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210157 138bc75d-0d04-0410-961f-82ee72b054a4
	PR libstdc++/61023
	* include/bits/stl_tree.h (_Rb_tree::_M_move_assign): Copy the
	comparison function.
	* testsuite/23_containers/set/cons/61023.cc: New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210159 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-07  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/61034
	* tree-ssa-alias.c (call_may_clobber_ref_p_1): Export.
	(maybe_skip_until): Use translate to take into account
	lattices when trying to do disambiguations.
	(get_continuation_for_phi_1): Likewise.
	(get_continuation_for_phi): Adjust for added translate
	arguments.
	(walk_non_aliased_vuses): Likewise.
	* tree-ssa-alias.h (get_continuation_for_phi): Adjust
	prototype.
	(walk_non_aliased_vuses): Likewise.
	(call_may_clobber_ref_p_1): Declare.
	* tree-ssa-sccvn.c (vn_reference_lookup_3): Also
	disambiguate against calls.  Stop early if we are
	only supposed to disambiguate.
	* tree-ssa-pre.c (translate_vuse_through_block): Adjust.

	* g++.dg/tree-ssa/pr61034.C: New testcase.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210160 138bc75d-0d04-0410-961f-82ee72b054a4
/cp
2014-05-07  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61080
	* pt.c (instantiate_decl): Avoid generating the body of a
	deleted function.

/testsuite
2014-05-07  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61080
	* g++.dg/cpp0x/deleted7.C: New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210161 138bc75d-0d04-0410-961f-82ee72b054a4
	PR libstdc++/61086
	* include/bits/stl_iterator.h (__normal_iterator::_M_const_cast):
	Remove.
	* include/bits/stl_vector.h (vector::insert, vector::erase): Use
	arithmetic to obtain a mutable iterator from const_iterator.
	* include/bits/vector.tcc (vector::insert): Likewise.
	* include/debug/vector (vector::erase): Likewise.
	* testsuite/23_containers/vector/requirements/dr438/assign_neg.cc:
	Adjust dg-error line number.
	* testsuite/23_containers/vector/requirements/dr438/
	constructor_1_neg.cc: Likewise.
	* testsuite/23_containers/vector/requirements/dr438/
	constructor_2_neg.cc: Likewise.
	* testsuite/23_containers/vector/requirements/dr438/insert_neg.cc:
	Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210162 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-07  Charles Baylis  <charles.baylis@linaro.org>

        * MAINTAINERS (Write After Approval): Add myself.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210164 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/
	PR tree-optimization/61095
	* tree-ssanames.c (get_nonzero_bits): Fix type extension in wi::shwi.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210181 138bc75d-0d04-0410-961f-82ee72b054a4
/cp
2014-05-07  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61083
	* pt.c (convert_nontype_argument): Protect all the error calls
	with complain & tf_error.

/testsuite
2014-05-07  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61083
	* g++.dg/cpp0x/sfinae50.C: New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210184 138bc75d-0d04-0410-961f-82ee72b054a4
Const-correctness of gimple_call_builtin_p

gcc/
2014-05-07  David Malcolm  <dmalcolm@redhat.com>

	* gimple.h (gimple_builtin_call_types_compatible_p): Accept a
	const_gimple, rather than a gimple.
	(gimple_call_builtin_p): Likewise, for the three variants.

	* gimple.c (gimple_builtin_call_types_compatible_p): Likewise.
	(gimple_call_builtin_p): Likewise, for the three variants.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210185 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/
	PR target/60884
	* config/sh/sh-mem.cc (sh_expand_strlen): Use loop when emitting
	unrolled byte insns.  Emit address increments after move insns.

gcc/testsuite/
	PR target/60884
	* gcc.target/sh/pr53976-1.c (test_02): Remove inappropriate test case.
	(test_03): Rename to test_02.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210187 138bc75d-0d04-0410-961f-82ee72b054a4
mksysinfo: Define CLONE flags.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210189 138bc75d-0d04-0410-961f-82ee72b054a4
rs6000: New attributes for load/store: "sign_extend", "update" and "indexed"

The new attributes replace the instruction types *_ext*, *_u, *_ux.

This simplifies all code that does not care about the addressing modes,
putting the burden on the code that does care (mostly the scheduling
descriptions for certain CPUs).

It fixes a few minor bugs in the process.

The "update" and "indexed" attributes are automatic for any insn that
has a MEM as operand 0 or 1.  Other insns have to set it manually, if
they do not like the default (which is "no").  Insns that are type
load/store/fpload/fpstore but have fewer than two operands need to set
it too, or the compiler will crash.  There are very few of those.

This tries not to change semantics anywhere; in particular, the string
and multiple instructions set both "update" and "indexed" (although
they are neither).


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210190 138bc75d-0d04-0410-961f-82ee72b054a4