Core: Making GeSiCa/SADC programming more robust by retrying
Revert "Core: Removing usleep in WrtCatch and F1 CATCH programming"

This reverts commit 959bbde0b334d13108f34e7dbe64d3ce21ce2347.
Scripts: Improve AcquManager init routine
Core: Retry GeSiCa programming if i2c init fails. Makes init more robust.
Core: Add SetTCSRunMode to RSupervise command list, needed for init
Core: Remove CATCH TDC usleeps, but keep register programming one (otherwise TDCs dont properly init)