ARM: tegra: don't exceed AVP limits when configuring PLLP

Based on the Tegra TRM, the system clock (which is the AVP clock) can
run up to 275MHz. On power on, the default sytem clock source is set to
PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to
408MHz which is beyond system clock's upper limit.

The fix is to set the system clock to CLK_M before initializing PLLP,
and then switch back to PLLP_OUT4, which has an appropriate divider
configured, after PLLP has been configured

Implement this logic in new function tegra30_or_later_adjust_pllp(),
which sets up PLLP and all PLLP_OUT* dividers, and handles the AVP
clock switching. Remove the duplicate PLLP setup from pllx_set_rate()
and adjust_pllp_out_freqs().

Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
[swarren, significantly refactored the change]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Remove duplicate adjustment of PLLP dividers from pllx_set_rate()
* Adjust PLLP_OUT1/PLLP_OUT2 dividers from clock_early_init() so that
  everything related to PLLP is set up at once.
* Initialize PLLP from a new common function tegra30_or_later_adjust_pllp()
  so the code isn't duplicated.
LATER: ARM: tegra: add support for more clocks on Tegra114

FIXME: work on this later after Tegra124 support.
FIXME: re-write commit description now it's been split up...

Some Tegra114 peripherals can take up to 8 different clock sources
(parents), including 4 new ones that don't exist on previous chips
(PLLC2/C3/MEM2/SRC2). Expand clock/PLL code/tables to support these
additional bits/sources.

Changes were made to some common code. Testing on Tegra30 and Tegra20
showed no changes in periph clock sources/divisors.

Also, peripheral clock sources that no longer exist on Tegra114 were
removed from the clock_periph_type table (CVE, TVDAC, etc.), and periphs
that are gone or not needed in early init are no longer brought out of
reset/enabled (FUSE, IRAMA/B/C/D, etc.).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v3:
* Undid change to assert on divisor value; the fix was applied to the
  wrong assert. The assert which should have been fixed was within the
  removed unused code.
v2:
- Fixed an assert test for a divisor value (s/b >0, not >=0)
- Remove some unused code
Revert "LATER: ARM: tegra: add support for more clocks on Tegra114"

This reverts commit 6cf0329f447d51e1ad5909d46f79cfd4756a4c93.
LATER: ARM: tegra: dalmore: add PMIC init for various peripherals

FIXME: work on this later after Tegra124 support.

These power rails are currently needed for kernel boot. This will be move
to a PMIC-specific driver (or even better moved to the kernel) at a later
date.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Revert "LATER: ARM: tegra: dalmore: add PMIC init for various peripherals"

This reverts commit 2e5b746676e5360325456184750e979726b4a009.
ARM: tegra: add/edit headers for Tegra124

These headers define the Tegra124 hardware. Add them to the usual
place.

Add Tegra124 chip ID/SKU ID definitions to common headers.

There's no real HW change on Tegra124 for 90% of the toys, so it might
make sense for a future patch to unify some of the content of these
files in a common location.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Put content directly into files in arch-tegra124/; don't put files there
  that simply include the real files in arch-tegra/.
* Removed unused emc.h, fuse.h.
* Added to arch-tegra/pmc.h rather than creating a new arch-tegra124/pmc.h,
  since some code already includes arch-tegra/pmc.h, and I didn't feel good
  about different code getting different versions of pmc.h.
* Remove error-inducing prototype for board_usb_init().
* Squashed in the other patch which edited arch-tegra/*.h, since they're
  both just adding/editing header files.
* Don't touch Tegra114 SPI header.
* Minor whitespace cleanup.
ARM: tegra: add SPL/AVP (arm720t) CPU files for Tegra124

This provides SPL support for Tegra124 boards - AVP early init, plus
CPU (A15) init/jump to main U-Boot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Convert to Kconfig-style make Makefiles.
* Update AVP/PLLP clock programming to match Tegra114.
* don't mangle (c) header in cpu.c.
* Remove leading space from debug() messages.
* Fix comment re: CPUPWRGOOD_TIMER
ARM: tegra: Add CPU (armv7) files for Tegra124

These files are for code that runs on the CPU (A15) on Tegra124 boards.
At this time, there is no A15-specific code here. The warmboot/LP0 files
aren't included as that code hasn't been ported yet.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Convert to Kconfig-style make Makefiles
* s/MASK_BITS_29_28/MASK_BITS_31_28/ to match earlier renaming patch
* Update AVP/PLLP clock programming to match Tegra114
ARM: tegra: add common (shared) CPU files

These files are used by both SPL and main U-Boot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: Add generic Tegra124 build support

Basic Tegra124 build support added - no specific board is targeted.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add DT files for Tegra124 and Venice2

These are fairly complete, and near-clones of Tegra114 Venice, with an
additional I2C port, and MMC address changes for Tegra124.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add Venice2 (Tegra124) board

These are the board files for Venice2 (Tegra124), plus the AS3722 PMIC
files. PMIC init will be moved to pmic_common_init later.

This builds/boots on Venice2, SPI/MMC/USB/I2C all work. Audio, display
and WB/LP0 are not supported yet.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Convert to Kconfig-style make Makefiles
* Fix boards.cfg sort order
* Remove most functional diffs (i.e. other than SoC name, valid values,
  etc.) between include/configs/tegra1[12]4-common.h
ARM: tegra: fix "bootp" issue for Tegra124 too

Fix the timeout issue after running "bootp" command in U-Boot console.

TXFIFOTHRES bits of TXFILLTUNING register should be set to 0x10 after a
controller reset and before RUN bit is se, (per technical reference
manual.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: fix Tegra124 SKU detection, and allow any SKU

Signed-off-by: Stephen Warren <swarren@nvidia.com>
cmd_pxe.c add any option for filesystem with sysboot uses generic load

Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
config: add config_distro_defaults.h

describe a set of default features that distros can rely on being available.
having this common definition means that distros can easily support systems
implementing them.

Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
pxe: implement fdtdir extlinux.conf tag

People who write (or scripts that auto-generate) extlinux.conf don't
want to know about HW-specific information such as FDT filenames. Create
a new extlinux.conf tag "fdtdir" that specifies only the directory where
FDT files are located, and defer all knowledge of the filename to U-Boot.
The algorithm implemented is:

==========
if $fdt_addr_r is set:
  if "fdt" tag was specified in extlinux.conf:
    load the FDT from the filename in the tag
  else if "fdtdir" tag was specified in extlinux.conf:
    if "fdtfile" is set in the environment:
      load the FDT from filename in "$fdtfile"
    else:
      load the FDT from some automatically generated filename

if no FDT file was loaded, and $fdtaddr is set:
  # This indicates an FDT packaged with firmware
  use the FDT at $fdtaddr
==========

A small part of an example /boot/extlinux.conf might be:

==========
LABEL primary
        LINUX zImage
        FDTDIR ./

LABEL failsafe
        LINUX bkp/zImage
        FDTDIR bkp/
==========

... with /boot/tegra20-seaboard.dtb or /boot/bkp/tegra20-seaboard.dtb
being loaded by the sysboot/pxe code.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v1 (relative to RFC): no change; just reposting as non-RFC

This patch depends on the following from Dennis Gilmore:
- cmd_pxe.c add any option for filesystem with sysboot uses generic load
- config: add config_distro_defaults.h
fs: fix generic save command implementation

Fix a few issues with the generic "save" shell command, and fs_write()
function.

1) fstypes[].write wasn't filled in for some file-systems, and isn't
   checked when used, which could cause crashes/... if executing save
   on e.g. fat/ext filesystems.

2) fs_write() requires the length argument to be non-zero, since it needs
   to know exactly how many bytes to write. Adjust the comments and code
   according to this.

3) fs_write() wasn't prototyped in <fs.h> like other generic functions;
   other code should be able to call this directly rather than invoking
   the "save" shell command.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
fs: implement infra-structure for an 'exists' function

This could be used in scripts such as:

if exists mmc 0:1 /boot/boot.scr; then
    load mmc 0:1 ${scriptaddr} /boot/boot.scr
    source ${scriptaddr}
fi

rather than:

if load mmc 0:1 ${scriptaddr} /boot/boot.scr; then
    source ${scriptaddr}
fi

This prevents errors being printed by attempts to load non-existent
files, which can be important when checking for a large set of files,
such as /boot/boot.scr.uimg, /boot/boot.scr, /boot/extlinux.conf,
/boot.scr.uimg, /boot.scr, /extlinux.conf.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
sandbox: implement fs_exists() and 'sb exists' shell function

This hooks into the generic "file exists" support added in the previous
patch, and provides an implementation for the sandbox test environment.

Signed-off-by: Stephen Warren <swarren@nvidia.com>