[bench] latest QEMU updates

The latest QEMU, which will be upstream, changes syntax once again.
We have to use "memory-backend-file" as the object type.

Signed-off-by: Nikolay Nikolaev <n.nikolaev@virtualopensystems.com>
Merge pull request #204 from virtualopensystems/backend

latest QEMU updates
Added lib/tlb.lua: Page-based address translation cache.

This can be used to cache page-based address translations, such as the
mappings between physical and virtual memory.

Modeled on a hardware Translation Lookaside Buffer:
http://en.wikipedia.org/wiki/Translation_lookaside_buffer
Use TLB cache (lib.tlb) in memory.virtual_to_physical().

Speeds up address translations. Measurable impact on loadgen
benchmark.
Merge pull request #205 from lukego/tlb2

Optimize memory.virtual_to_physical() with software TLB
Revert "intel10g optimization: no register reads for TX/RX."

That change needs more test/debug.
Merge pull request #206 from lukego/revert-intel10g

Revert "intel10g optimization: no register reads for TX/RX."
net_device.lua: Cache address translations with lib.tlb.

This is a major speedup but the main issue with the existing code
seems to be that it failing to JIT.
Merge pull request #207 from lukego/vhost-user-tlb

net_device.lua: Cache address translations with lib.tlb.
intel10g: Adapt receive/can_receive to not annoy LuaJIT.

This is based on Alex Gall's implementation on the mailing list:

  https://groups.google.com/d/msg/snabb-devel/JFFxbBOrG8k/Aek4VSsl5JwJ
Merge pull request #208 from lukego/intel10g-opt-fix

intel10g: Adapt receive/can_receive to not annoy LuaJIT.
net_device: Optimized for 1GB huge pages.

translate_physical_addr() and map_from_guest() switched from the
software TLB to a simple one-element cache of the most recent
referenced page. (With 1GB pages there is normally only one page so
the cache should always hit.)

map_to_guest() removed because it was not used.
memory.virtual_to_physical(): drop use of TLB cache.
bench_env/include_checks.sh: Don't check hugepages.

This test is not appropriate with 1GB HugeTLBs.
Merge pull request #211 from lukego/hugetlb1G

1G HugeTLB optimizations
link: % size -> band
intel/loadgen: cache link.receive, do local
intel10g: % -> band
tlb: cache bit.rshift
intel/loadgen: cache can_transmit, transmit