fb/ramnva3: WIP link training unit

XXX: Multiple partitions
fb/ramnva3: Use ram->base structs instead of local structs

This will ease the use of generic timing and MR generation bits later
fb/ramnva3: Ressurect timing calculation code
fb/sddr3: Expand MR generation with various bits
fb/sddr2: Generate MR values
fb/nva3: WIP Start on some reclocking bits
pwr/memx: WIP Wait for VBLANK if desired
WIP train external hook
fb/ramnva3: WIP support for DDR2 reclocking
fb/ramfuc: Support strided regs
fb/ramnva3: WIP Per-partition regs
fb/ramnva3: Initialise PART_PM_SEL
fb/ramnva3: WIP try to avoid flicker on reclocking
pwr/memx: Return execution time
pwr/nva3: DROP: regenerate microcode