power: qpnp-charger: take into account charge path priority

On the SMBB peripheral there is a possibility of having
both the USB and DC input being connected at the same time.
In this situation there is a requirement to be able to communicate
to userspace services that the higher priority input was
inserted so appropriate action can be taken.

This is achieved as follows:

1. If DC has the higher priority, the USB input
current limit will be reduced to 100 mA to avoid
charging from the USB path.

2. If USB has priority the DC input current
limit will be reduced to 100 mA to avoid charging
from the DC path.

3. Upon the removal of the priority charge path
the secondary charge path input current limit
will be restored to allow charging.

Change-Id: Ib2ad561ef414eca98f1b3a003aaa0eea1fec8269
CRs-Fixed: 637169
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
Signed-off-by: Gopal G Goberu <ggober@codeaurora.org>
ASoC: wcd9306: Update condition to disable HPH PA after impedance detection

For headsets with threshold on mic, the flag hph_pa_dac_state gets
cleared once they are re-inserted into headphone jack with hph pas
are still ON. This causes impedance detection to disable the PA after
impedance computations. This will result into audio mute. Avoid the
audio mute by updating the condition to disable PAs.

CRs-Fixed: 694315
Change-Id: Ib7ab495485a321333c1b8b211559adc7c164735c
Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
Merge "ASoC: wcd9306: Update condition to disable HPH PA after impedance detection"
power: qpnp-charger: Add VCHG_LOOP_DBC_BYPASS property

Add a property VCHG_LOOP_DBC_BYPASS in battery power supply. It is used
for enabling/disabling the buck VCHG_LOOP debouncer timer.

Change-Id: If3f1ecb56abe2319e9defb6ef03a83b972632ef4
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
Merge "power: qpnp-charger: Add VCHG_LOOP_DBC_BYPASS property"
Merge "power: qpnp-charger: take into account charge path priority"
power: qpnp-bms: add a delay for timing requirement

A delay of 2 sleep clock cycles (~60 microseconds) is found to be needed
between locking the bms output registers and reading the coulomb counter.
Without this delay, there can be a potential SPMI transaction failure
where the peripheral fails to respond.

As a safety measure, also add error handling code to abort the current SOC
calculation if a read fails.

CRs-Fixed: 720880
Change-Id: Ia632e31202791afa82ff4b49a8eaa334fd22da8f
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
Merge "power: qpnp-bms: add a delay for timing requirement"
ASoC: msm: Fix ADM GET PARAM callback.

Add size check on inband get param call and do
not process inband if RTAC is active.

Change-Id: I2c099f5ea254a214f224dda556773a7fe6754fe5
CRs-fixed: 548397
Signed-off-by: Ben Romberger <bromberg@codeaurora.org>
Merge "ASoC: msm: Fix ADM GET PARAM callback."