ARM: sunxi: Add earlyprintk support for R_UART (sun6i/sun8i)

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
serial: 8250_dw: Add optional reset control support

The Allwinner A31 and A23 SoCs have a reset controller
maintaining the UART in reset by default.

This patch adds optional reset support to the driver.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
wdt: sunxi: make the register offsets configurable

The Allwinner A31 and A23 SoCs have a similar watchdog unit to the
ones found in the A10 SoC, but some of the register offsets have
been rearranged.

This patch adds a structure which contains the various register
offsets needed, and shall be tied to device compatibles.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
wdt: sunxi: Add Allwinner sun6i-a31 compatible

This patch adds the compatible and associated register offsets for
the watchdog unit found in the A31 SoC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Fix gate indexing for sun6i-a31-apb0-gates

sun6i-a31-apb0-gates supports using clock-indices for holes between
individual gates. However, the driver passes the number of gates
registered in clk_data->clk_num, which of_clk_src_onecell_get uses
to recognize the range of valid indices a consumer can use.

This patch makes the driver pass the maximum gate index + 1, so
of_clk_src_onecell_get does not complain about indices greater
than gates registered.

This was tested on the A23 SoC, which has a similar APB0 clock,
but has holes for gates to removed IP blocks.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Fix PLL6 calculation on sun6i

The N factor for PLL6 counts from 1 to 32, as specified in the A23
manual, and shown in Allwinner's original code.

This patch fixes the N factor in the clock driver, as well as the
comment describing it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Add A23 clocks support

The clock control unit on the A23 is similar to the one found on the A31.

The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones
on the A31, but some outputs are missing.

The main CPU PLL (PLL1) however is like that on older Allwinner SoCs, such
as the A10 or A20, but the N factor starts from 1 instead of 0.

This patch adds support for PLL1 and all the basic clock gates.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Add basic USB clock support for A23

The A23 has similar USB clocks to the A31. The difference
is the A23 has less USB controllers and PHYs, but also it
has support for HSIC.

HSIC clock support is not implemented at the moment, as we
do not have any hardware using it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Add A23 APB0 support to sun6i-a31-apb0

The A23 has an almost identical PRCM clock tree. The difference in
the APB0 clock is the smallest divisor is 1, instead of 2.

This patch extends the sun6i-a31-apb0 driver to take divider tables
associated to compatibles, and adds a compatible for the A23 variant.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
pinctrl: sunxi: Add support for A23 PIO and R_PIO controllers

The A23, like the A31, has 2 pin controllers. This patch adds support
for both of them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
mfd: sun6i-prcm: Add support for Allwinner A23 PRCM

The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC.
The differences are the AR100 clock can no longer be modified,
and the APB0 clock has different divisors.

This patch adds a compatible with a modified subdevice list for
the A23.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: sunxi: Introduce Allwinner A23 support

The Allwinner A23 is a dual-core Cortex-A7-based SoC. It re-uses most of
the IPs found in previous SoCs, notably the A31.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: sunxi: Add Allwinner A23 dtsi

The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
and a Mali-400MP2 GPU.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: sun8i: dt: Add Ippo-q8h v5 support

The Ippo-q8h is a tablet board commonly found in cheap Android tablets
with A23 SoCs. There are at least 2 versions of the board, with
different peripherals, such as WiFi chips.

This patch add support for v5 of such boards, which has a ESP8089 WiFi
chip connected to mmc1.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>