ERC and DRC passed. Added ground vias everywhere. Fixed 0.1in breakout header by making new symbol, should be able to drop in a proper header if we want. Changed order of IO pins on sch to make sense and swapped four of the IO pin signals for ease of routing. Fixed tNames on board so labels align with the right parts. Added voltage to caps in sch. Tidied up. Added board title on tnames layer. Andrew is free to fix voltage 3.3vd, 2.85va, 2.86vd with polygons for OCD & beauty reasons if his heart so desires.
Exported all libraries.
Fresh libraries export. Sent email to Andrew with notes.
Trying to fix merge conflict.