[mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V

Summary:
These processors will only be available for the integrated assembler at
first (CodeGen will emit a fatal error saying they are not implemented).

The intention is to work through the existing instructions and correctly
annotate the ISA they were added in so that we have a sufficiently good
base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain
instructions and I believe it is best to define ISA's using set-union's
as far as possible rather than using set-subtraction.

Reviewers: vmedic

Subscribers: emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D3569
Remove "CH_ECK" line (which is ignored) from test after r154191.

r154191 switched to atexit() instead of global destructors, so the intent
was probably to check for _GLOBAL__D_a _not_ being in the output. There already
is a line for _ZN3barD1Ev further up, so just remove the CH_ECK line referring
to that.

The only circumstance in which clang emits _GLOBAL__D_a destructor symbols is
for -fapple-kext, and that is tested by test/CodeGenCXX/cxx-apple-kext.cpp.