Optimize merging of scalar loads for 32-byte vectors [X86, AVX]

Fix the poor codegen seen in PR21710 ( http://llvm.org/bugs/show_bug.cgi?id=21710 ).
Before we crack 32-byte build vectors into smaller chunks (and then subsequently
glue them back together), we should look for the easy case where we can just load
all elements in a single op.

An example of the codegen change is:

From:

vmovss  16(%rdi), %xmm1
vmovups (%rdi), %xmm0
vinsertps       $16, 20(%rdi), %xmm1, %xmm1
vinsertps       $32, 24(%rdi), %xmm1, %xmm1
vinsertps       $48, 28(%rdi), %xmm1, %xmm1
vinsertf128     $1, %xmm1, %ymm0, %ymm0
retq

To:

vmovups (%rdi), %ymm0
retq

Differential Revision: http://reviews.llvm.org/D6536



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223518 91177308-0d34-0410-b5e6-96231b3b80d8
Reverting r223513 and r223514.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223520 91177308-0d34-0410-b5e6-96231b3b80d8
Remove dead code. We are only lazy about functions with bodies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223521 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding sub/and/or reg, imm forms

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223522 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Relocating logical instructions and templates later in the td file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223523 91177308-0d34-0410-b5e6-96231b3b80d8
Recommit of r223513 and r223514.

Reviewed at http://reviews.llvm.org/D6488



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223532 91177308-0d34-0410-b5e6-96231b3b80d8