Power: Correct little-endian e500v2 GPR frame offsets

This change corrects GPR frame offset calculation for the e500v2
processor.  On this target, featuring the SPE APU, GPRs are 64-bit and
are held in stack frames whole with the use of `evstdd' and `evldd'
instructions.  Their integer 32-bit part occupies the low-order word and
therefore its offset varies between the two endiannesses possible.

	* rs6000-tdep.c (rs6000_frame_cache): Correct little-endian GPR
	offset into SPE pseudo registers.