Reorg

# Reorganization Complete
Successfully completed the code reorganization. This code matches, more or less, the diagram in Fig. 5.24, module for module. The only diversions are a few additional control lines for the JR and JAL routines, and sticking the HI and LO registers for the MULT and DIV directly in the ALU itself.

All tests are passed in the README, and it produces the correct value of 5040 for Factorial(7).

The clock time is 20 ns. A sim time of 1760 ns will produce the output for factorial.

It should be easier to make a pipelined spec out of this by following the diagram on Fig. 6.21. Unfortunately there is little time left to do so. I have a couple more papers and an exam in the next couple days which may take up all my remaining time through Wednesday.