APPLIED: usb: ci_udc: fix ci_flush_{qh,qtd} calls in ci_udc_probe()

ci_udc_probe() initializes a pair of QHs and QTDs for each EP. After
each pair has been initialized, the pair is cache-flushed. The
conversion from QH/QTD index [0..2*NUM_END_POINTS) to EP index
[0..NUM_ENDPOINTS] is incorrect; it simply subtracts 1 (which yields
the QH/QTD index of the first entry in the pair) rather than dividing
by two (which scales the range). Fix this.

On my system, this avoids cache debug prints due to requests to flush
unaligned ranges. This is caused because the flush calls happen before
the items[] array entries are initialized for all but EP0.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
APPLIED: usb: ci_udc: don't assume QTDs are adjacent when transmitting ZLPs

Fix ci_ep_submit_next_request()'s ZLP transmission code to explicitly
call ci_get_qtd() to find the address of the other QTD to use. This
will allow us to correctly align each QTD individually in the future,
which may involve leaving a gap between the QTDs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
APPLIED: usb: ci_udc: lift ilist size calculations to global scope

This will allow functions other than ci_udc_probe() to make use of the
constants in a future change.

This in turn requires converting the const int variables to #defines,
since the initialization of one global const int can't depend on the
value of another const int; the compiler thinks it's non-constant if
that dependency exists.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
APPLIED: usb: ci_udc: fix items array size/stride calculation

2 QTDs are allocated for each EP. The current allocation scheme aligns
the first QTD in each pair, but simply adds the struct size to calculate
the second QTD's address. This will result in a non-cache-aligned
addresss IF the system's ARCH_DMA_MINALIGN is not 32 bytes (i.e. the
size of struct ept_queue_item).

Similarly, the original ilist_ent_sz calculation aligned the value to
ARCH_DMA_MINALIGN but didn't take the USB HW's 32-byte alignment
requirement into account. This doesn't cause a practical issue unless
ARCH_DMA_MINALIGN < 32 (which I suspect is quite unlikely), but we may
as well fix the code to be explicit, so it's obviously completely
correct.

The new value of ILIST_ENT_SZ takes all alignment requirements into
account, so we can simplify ci_{flush,invalidate}_qtd() by simply using
that macro rather than calling roundup().

Similarly, the calculation of controller.items[i] can be simplified,
since each QTD is evenly spaced at its individual alignment requirement,
rather than each pair being aligned, and entries within the pair being
spaced apart only by structure size.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
APPLIED: usb: ci_udc: remove controller.items array

There's no need to store an array of QTD pointers in the controller.
Since the calculation is so simple, just have ci_get_qtd() perform it
at run-time, rather than pre-calculating everything.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
APPLIED: usb: ci_udc: don't memalign() struct ci_req allocations

struct ci_req is a purely software structure, and needs no specific
memory alignment. Hence, allocate it with calloc() rather than
memalign(). The use of memalign() was left-over from when struct ci_req
was going to hold the aligned bounce buffer, but this is now dynamically
allocated.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
APPLIED: USB: gadget: atmel: zero out allocated requests

A UDC's alloc_request method should zero out the newly allocated request.
Ensure the Atmel driver does so. This issue was found by code inspection,
following the investigation of an intermittent issue with ci_udc, which
was tracked down to failing to zero out allocated requests following some
of my changes. All other UDC drivers already zero out requests in one
way or another.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
APPLIED: usb: ci_udc: use var name ep/ci_ep consistently

Almost all of ci_udc.c uses variable name "ep" for a struct usb_ep and
"ci_ep" for a struct ci_ep. This is nice and consistent, and helps people
know what type a variable is without searching for the declaration.
handle_ep_complete() doesn't do this, so fix it to be consistent.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
i2c: tegra: use repeated start for reads

I2C read transactions are typically implemented as follows:

START(write) address REPEATED_START(read) data... STOP

However, Tegra's I2C driver currently implements reads as follows:

START(write) address STOP START(read) data... STOP

This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board,
leading to corrupted read data in some cases. Fix the driver to chain
the transactions together using repeated starts to solve this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Yen Lin <yelin@nvidia.com>
i2c: tegra: write clean data to TX FIFO

The Tegra I2C controller's TX FIFO contains 32-bit words. If the final
FIFO entry of a transaction contains fewer than 4 bytes, the driver
currently fills the unused FIFO bytes with uninitialized data. This can
be confusing when reading back the FIFO content for debugging purposes.

Solve this by explicitly initializing the variable containing FIFO data
before filling it (partially) with data. With this change,
send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e.
read) branch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Yen Lin <yelin@nvidia.com>
i2c: tegra: dump alen in debug statements

Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump
the address length (alen) too, so the address value can be correctly
interpreted.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Yen Lin <yelin@nvidia.com>
ARM: tegra: enable DFU too

Enable DFU protocol support (via the "dfu" command) on Tegra boards where
USB device/gadget mode is enabled.

This relies on a number of fixes to the ci_udc HW driver and DFU protocol
code.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
TEMP HACK: enable ext4 write for DFU testing
test: dfu: cleanup before execution

Call cleanup() before running tests too. If a previous test was CTRL-C'd
some stale files may have been left around. dfu-util refuses to receive
a file to a filename that already exists, which results in false test
failures if the files aren't cleaned up first.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
test: dfu: add some more test cases

On Tegra, the DFU buffer size is 1M. Consequently, the 8M test always
fails. Add tests for the 1M size, and one byte less as a corner case,
so that some large tests are executed and expected to pass.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
dfu: fix readback buffer overflow test

The buffer is too small if it's < size to read, not if it's <= the size.
This fixes the 1MB test case on Tegra, which has a 1MB buffer.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
LOCAL: test: dfu: reduce max test binary size

Tegra's DFU buffer is smaller than 8M. Remove that test case since we
know it will fail.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
FIXME: BOOTP retry timeout improvements

Signed-off-by: Stephen Warren <swarren@nvidia.com>