Update at Mon May 26 09:55:12 EDT 2014 by tim
Update at Tue May 27 19:10:21 EDT 2014 by tim
Update at Thu May 29 10:52:52 EDT 2014 by tim
Update at Fri May 30 14:41:25 EDT 2014 by tim
Update at Sat May 31 14:50:58 EDT 2014 by tim
Correction to the clocktree script to handle cells such as tiehi/
tielo that have no inputs, instead of generating an error and
exiting.
Update at Wed Jul  9 12:00:47 EDT 2014 by tim
Merge branch 'master' into work
Additional diagnostic statements printed in the STA tool.
Update at Sat Jul 12 14:18:44 EDT 2014 by tim
Merge branch 'master' into work
Fixed an error that causes vesta to crash if it has bad input and
cannot find a valid netlist.
Corrected an error in blifFanout that causes a crash if the gate
strength changes from a 1-character suffix (e.g., "1") to a
2-character suffix (e.g., "10").
Added support for structural verilog in-line, pending update of
yosys to revision 0.3.1.
Update at Thu Jul 17 08:34:09 EDT 2014 by tim
Merge branch 'master' into work
Updated synthesis checks on yosys version to capture the newest
revision string format of <major>.<minor>.<rev>+<commit>
This allows qflow to handle syntax changes made by a specific
source code commit.
Update at Thu Sep 18 09:34:36 EDT 2014 by tim
Merge branch 'master' into work
Corrected an error that prevents qflow from working with qrouter
version 1.3.0.