dpram_altera: make the instantation even more generic

When the device familly is not specified, modelsim chose the
default Stratix familly. Then, it throws up:

 Error: BYPASS value for CLOCK_ENABLE_INPUT_A is not supported in
 Stratix device family

This patch let clock_enable_xxx parameters get their default value.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
bench: fix wb_bfm_transactor signal name

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
wb_port_arbiter: initialize ff1 to zero

This might go through the function undefined otherwise
wb_port_arbiter: fix cache coherency during wb block write

Multiples write can occur during a single write block cycle.

Old code triggers a buffer write on the rising edge of wb_cyc.
This only works with single write cycles.

This patch signals that a write have happend to all ports
on every wb_ack during the write block cycle.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
wb_port: fix read-after-write bug

if a read to an address already in the burst cache
would immediately occur after a write to the same
burst cache, the address from the write would be
used to fetch the read data.

This fixes it by disabling support for write bursts
(which were broken in either case) and deassert the
write to the burst cache when the write is acked.
WIP : refactoring