First steps towards reorganising the TG68MiniSOC project.
Hello World DE1 project working.
Hello World now works on the EMS11-BB21
Migrated parts of the codebase to generic RAM.
Replaced more vendor-specific RAM definitions with generic versions.
DE1 project now tested and working with no explicitly Altera-specific code except the PLL.  Porting to Xilinx should now be straightforward.
VGA board pin mappings for EMS11-BB21 tested and working.
SOC project working on DE1
First attempt at getting the SOC working on Xilinx.  Build completes, but not yet working.
Added SDRAM controller UCF file to place sdata_reg in IOBs.
Added missing Clock_50to100 xilinx files
More steps towards getting the project working on EMS11_BB21.  Need to concentrate further on multicycles.
Added Firmware and RTL directories to SOC
Started SanityCheck project, HelloWorld equivalent on DE1 works.
Fixed writecache bug in SDRAM controller, worked on SanityCheck project.
Added missing FPGA files for EMS11-BB21
added missing .xcf file
Added overrun and frameerror flags to SOC's UART.
Bug fix to reads from peripheral registers which was causing incoming data to be lost from UART and probably PS/2
Removed explicit sizes from branches in bootstrap code.