hdl: add RX and TX meta FIFOs

These FIFOs will be used to store timestamp, modulation, and coding data
on a per packet basis. The meta header format is described in the
following commit.
hdl: timed RX and TX

Timed RX and TX is enabled when nios_gpio bit 9 is set. RX and TX samples
are now packetized so now the first 16 bytes of every 512 byte or 1024
byte GPIF transcations contain metadata. The HDL state machine will not
wait for the TX time to match that of any TX packet, and it will insert
timestamps into RX packet streams.
hdl: add time tamer

This tamer is an Avalon compatible core that snapshots the RX and TX timestamp
counters whenever the least significant byte of the 64bit registers is read.
The RX LSB is at offset 0, and the TX LSB is at offset 8. If any register within
the time tamer address space is writen to, the core will output a sync signal
that the rest of the system will interpret as a signal to synchronize resetting
the RX and TX timestamp counters to 0.
hdl: minor corrections needed to get testbench working again
nios: rework register mapping

This commit adds support for time tamer register and introduces a command
parsing loop that allows for multiple reads/write per uart_cmd packet.
libbladeRF: add variable length memory register reads/writes

This commit adds support for performing an arbitrary number of reads/writes when
accessing memory mapped registers inside of Nios.
The 8 byte timestamp counters can now be read in 2 uart_cmd packets instead of 8.
libbladeRF: add the ability to query RX and TX timestamp counters
hdl: Cleanup timing issues and synchronization.

libbladeRF: Fix bad merge resolution.
hdl: Fixing time comparisons and meta_enable

Removed calls to to_integer() for 64-bit numbers since they don't work correctly.

Added the meta_enable bit to the GPIO pins for simulation.
meta_tx_fifo: enable fifo underflow and overflow checking
hdl: fix off by ones in packet counters and position of timestamp in header
tb: add configurable RX and TX options

This commit introduces paramatrized testbenching of RX/TX with and without
meta timestamps.
hdl: check packet to ensure it is set to occur in the future

This commit introduces some basic error checking. Packets are now checked to
ensure that their timestamps haven't already passed. This ensures that
fifo_reader will not get stuck waiting for the timestamp counter to wrap around.

This commit does not protect against two overlapping packets being schedule in
the future. Such packets would also lock fifo_reader. At the moment we'll assume
software ensures that packet timestamps are non-overlapping.
libbladeRF: initialize status variable to do away with warnings
libbladeRF: add generic read/write bytes functions to accessig "GPIO" registers
hdl: prepare NiOS for expansion board upgrade

This commit adds a secondary select like to the DAC SPI controller (the
secondary select line is meant for the expansion board). Two parallel PIO ports
are are also added. One is an in/out PIO for expansion board GPIO values and the
other is for controlling the direction of the aforementioned PIO.
hdl: rework the embedded NiOS code, add XB support

This commit reworks the current NiOS code to make it more managable. The "GPIO"
device now have a register map that is defined by the variable gdev_lut:

Offset : Device
[ 0]   :  GDEV_GPIO
[ 4]   :  GDEV_IQ_CORR_RX
[ 8]   :  GDEV_IQ_CORR_TX
[12]   :  GDEV_FPGA_VERSION
[16]   :  GDEV_TIME_TIMER
[34]   :  GDEV_VCTXCO
[36]   :  GDEV_XB_LO (XB_SPI)
[40]   :  GDEV_EXPANSION
[44]   :  GDEV_EXPANSION_DIR
libbladeRF: move VCTCXO into GPIO device register map.

The VCTCXO device is similar to a few other devices so it is now part of the
GPIO device register map. This commit changes the way libbladeRF accesses
the VCTCXO.
libbladeRF: add SPI support to expansion board
libbladeRF: add GPIO value support to expansion board

Reading and writing the GPIO register will not correspond to the expansion board
headers.