verilog: Add support for SystemVerilog

* Includes support for data types introduced in SystemVerilog and "class".
* Add basic SystemVerilog test unit.
verilog: Add no-context test cases

Guarantees that parser does not fail when finding tags without a context.
verilog: Add support for SystemVerilog programs

Also include support for lifetime keywords "static" and "automatic", which can
also be part of program declarations. These keywords are currently ignored.
verilog: Add support for SystemVerilog interface
verilog: Do not require context to find a new block

Process named blocks defined outside the context of a container (e.g. if it is
defined in a file to be included within other files). To achieve this,
currentContext is created in the initial parser call.
verilog: Add support for SystemVerilog assertions
verilog: Use tokens to store extra identifier information
verilog: Support functions with range or type defined
verilog: Improve support of functions and tasks in SystemVerilog

In SystemVerilog function, task, etc declarations support a simple typeless port
declaration such as:

function mult(a, b);

Add support for such port declarations by searching for any non-keyword tag,
ignoring its direction and type. The same algorithm is also used in task
declarations.

Also add support for extern functions and tasks.
verilog: Create dropContext() function
verilog: Add support for SystemVerilog typdef
verilog: Add support for SystemVerilog package
verilog: Add support for SystemVerilog covergroup
verilog: Only call tagNameList in variable-like tags

Only variable-like tags can be defined in a name list split by commas, so move
all variable declaration related code to inside tagNameList function and only
call it when such kinds are found.
docs: Include SystemVerilog in new parser list
verilog: Do not add tags with empty name

Check for the existence of a name in the token before creating a tag, in case
something unexpected happens where this createTag() is called.
Automatically re-generate Makefile when Makefile.in changed

This avoids having an out of date copy of the Makefile when it source,
Makefile.in, changed.

The implementation here only works with GNU Make, but it should not
have undesirable effects with other Make implementations (if we ever
support them).
Print all verbose output to stderr

Signed-off-by: Masatake YAMATO <yamato@redhat.com>
units: Turn --verbose option on for debugging

Signed-off-by: Masatake YAMATO <yamato@redhat.com>
Merge pull request #171 from vhda/verilog/system-verilog

Verilog/system verilog