[RAM] Fixed ram index out of range problem
[ALU,ALUControl,OutputControl] Implemented addi instruction

[ALU] New addi entry in output switch
[OutputControl] Added addi code in RegWrite, ALUOp, RegDst switches
[ALUControl] Decode new ALUOp addi entry
[ProgramCounter,InstructionMemory] Fixed pick up of first instruction

[ProgramCounter] Before first clock rising edge output set to -4
[InstructionMemory] If Address is a negative number set the output to -1 (0 gives problems because the arith OpCode is all 0. All 1 is not mapped)
[Registers] Exclude writing X to register before first clock raise
[InstrucionMemory, Registers] Cleanup initializations
[Registers,MIPS,OutputControl] Dirty fix to a problem during writeback due to no delay simulation

[Registers] Delayed RegWrite with the transport model
[OutputControl] When the previous instruction set RegWrite to 1, the current writes the data in the wrong register because RegWriteIn is still not updated. This commit avoids this situation setting RegWrite to 0 overy clock cycle (yeah is dirty)
[MIPS] Updated declaration and statement of OutputControl
Added some useful scripts and data example