msm: mdss: Request max register bus bandwidth for PP LUTs during resume

There are a couple postprocessing features that are LUT based features,
and they require a lot of register accesses to configure the hardware.
During the first resume display commit, when all registers are
reconfigured, if any of the LUT based PP features are enabled, then we
will request maximum bus bandwidth to speed up the accesses.

Change-Id: I17a8c0f563db3a3715c170dbcd5666b0ee567b01
Signed-off-by: Benet Clark <benetc@codeaurora.org>

ARM: dts: msm: Reading MDP offsets from device tree for PP functions.

The register address offset values are currently stored in macro
variables. These are now being moved to device tree. These addresses
cannot be calculated in cases of targets which have single DSPP like
8226.

The required register address offset values are added to the
respective target device tree files. The address validation
functions corresponding to PP are modified to read the values from
these newly added device tree entries.

8x10 target does not require this change as it uses MDP3
architecture.

Change-Id: I9387c8fadc36e3bbaceb51b243d3a9537250a3be
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>

msm: mdss: remove obsolete method of mixer register read/writes

Starting apq8084, mixer offsets have changed compared to previous
chip-sets. Some of the code is still using old method of reading
and writing to mixer registers which leads to incorrect hw programming.
Replace these mixer register read/writes with working method.

CRs-Fixed: 564273
Change-Id: I2aa1c5d24c6a1c5b89f77bd8d450c0831dd720b7
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>

msm: mdss: Fix CSC programming for VIG3 pipe

CSC programming assumes that pipe numbers are symmetric for same
type. This assumption is not valid with APQ8084 and leads to skipping
of CSC programming for VIG3 pipe. Fix this by using helper APIs to
find out if pipe is VIG or not rather than directly manipulating data
structures.

Change-Id: I130ee3994d1f5c5a96e644f8095c75d2189fbdda
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>

msm: mdss: fix bandwidth vote release for dual-dsi cmd mode panels

For dual-dsi command mode panels, bandwidth(bw) vote is supposed to be
released once ping-pong done interrupt for both controller is received.
In current implementation, if secondary ctl finishes last, which is the
case most of the times, then bw release is called using secondary ctl.
But bw is calculated/stored using main ctl because of which bw vote is
never released as expected. Fix this by releasing bw vote using main ctl.

Change-Id: Iadbd150ed6a35478da2cb376e29b01e579a526b8
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>

mdss: calculating length based on offsets from dts

If the len values are not mentioned in the device tree, then
calculate the length based on the corresponding offsets
Plus split mdss_sspp into: sspp_vig, sspp_rgb and sspp_dma.
Because in 8092, the lengths are different. Therefore, they
should be separate lengths in the generic implementation.

Change-Id: I0f83ffae15d1ae3e92a01f7f23215c94b23065c7
Signed-off-by: Zohaib Alam <zalam@codeaurora.org>

ARM: dts: msm: Removing len parameters for mdss device tree

The len parameters for sizes of SSPP, DSPP, CTL and Mixer
interfaces are not used in the code anymore.

Removing those parameters from device tree.

Change-Id: Ib49a3d79c27f3291d942e0f36fcb78da93eb43f2
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>