[UPSTREAM] ALSA: hda - initialize audio InfoFrame to be all zero

This patch initialized the local audio InfoFrame variable 'ai' to be all zero,
thus the data bytes will indicate "Refer to Stream Header" by default.

Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
(cherry picked from commit caaf5ef9493f72390905f1e97b310b8906d32dac)
link: http://git.kernel.org/cgit/linux/kernel/git/tiwai/sound.git/commit/?id=caaf5ef9493f72390905f1e97b310b8906d32dac

Change-Id: Ie3cd75d41422f800f6cf525d597663a31c9ad416
Reviewed-on: https://chromium-review.googlesource.com/191239
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
Tested-by: AleX Kelly <alex.kelly@intel.com>
Commit-Queue: AleX Kelly <alex.kelly@intel.com>
[DO NOT REBASE] drm/i915: Fix forcewake counts for gen8

Sometimes generic driver code gets forcewake explicitly by
gen6_gt_force_wake_get(), which check forcewake_count before accessing
hardware. However the register access with gen8_write function access
low level hw accessors directly, ignoring the forcewake_count. This
leads to nested forcewake get from hardware, in ring init and possibly
elsewhere, causing forcewake ack clear errors and/or hangs.

Fix this by checking the forcewake count also in gen8_write

v2: Read side doesn't care about shadowed registers,
    Remove __needs_put funkiness from gen8_write. (Ville)
    Improved commit message.

References: https://bugs.freedesktop.org/show_bug.cgi?id=74007
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit e9dbd2b20201b49b04476d2e5763faa822967913)

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: I206da85c73a166c9351dd918d97dc18f8db8e48a
Reviewed-on: https://chromium-review.googlesource.com/191307
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
Commit-Queue: James Ausmus <james.ausmus@intel.com>
[DO NOT REBASE] drm/i915: Do forcewake reset on gen8

When we get control from BIOS there might be mt forcewake
bits already set. This causes us to do double mt get
without proper clear/ack sequence.

Fix this by clearing mt forcewake register on init,
like we do with older gens.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 0a089e3355d77f758e46db54a0a81d4b58a28cc3)

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: I8909107ca82f792462415c0d04aa3545103c5116
Reviewed-on: https://chromium-review.googlesource.com/191308
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
Commit-Queue: James Ausmus <james.ausmus@intel.com>
[DO NOT REBASE] drm/i915: Disable semaphore wait event idle message on BDW

According to BSpec we need to always set this magic bit in ring buffer
mode.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 295e8bb73a4785b65db6655fbf6ad57c4177b551)

Conflicts:
	drivers/gpu/drm/i915/intel_pm.c

(cherry picked from commit 7bd4a50427011b9e89e3915213f4536a1821dd08)

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: I6048ccad66ab744e9f79519428615516b79c9240
Reviewed-on: https://chromium-review.googlesource.com/191309
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
Commit-Queue: James Ausmus <james.ausmus@intel.com>
[DO NOT REBASE] drm/i915: Implement WaDisableSDEUnitClockGating:bdw

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 4f1ca9e94057de098d65bc7477e8f89dd51609aa)

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: Iaf5bdfc4ff93891f55e5fe739ec2f2f29b50403e
Reviewed-on: https://chromium-review.googlesource.com/191330
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
Commit-Queue: James Ausmus <james.ausmus@intel.com>
[DO NOT REBASE] drm/i915: Add a partial instruction shootdown workaround on Broadwell.

I believe this will be necessary on production hardware.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Fix whitespace fail spotted by checkpatch. Also add missing
:bdw w/a tag that Ville spotted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit c8966e1058e1e8ae2eec4211157847032829697a)

Conflicts:
	drivers/gpu/drm/i915/intel_pm.c

(cherry picked from commit 4838d9b5df27b82ae286543bcac4ceaebd073155)

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: I5d66de18a9ca060e1a3893b02661e90583ec3808
Reviewed-on: https://chromium-review.googlesource.com/191331
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
Commit-Queue: James Ausmus <james.ausmus@intel.com>
[DO NOT REBASE] drm/i915: Add thread stall DOP clock gating workaround on Broadwell.

Ben and I believe this will be necessary on production hardware.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
[danvet: Shuffle lines to group all ROW_CHICKEN writes and add a
cautious comment that this might not be needed on production hw.]
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 1411e6a57a1836ba8a3d4f17c8733b2fbaf0f005)

Conflicts:
	drivers/gpu/drm/i915/intel_pm.c

(cherry picked from commit e63710c308ba6b47e0d5cb5f4b997f4846a76ca4)

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: I7b4e16d306663a4e31608f7eac40c1721e58723a
Reviewed-on: https://chromium-review.googlesource.com/191332
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
Commit-Queue: James Ausmus <james.ausmus@intel.com>
[DO NOT REBASE] drm/i915/bdw: The TLB invalidation mechanism has been removed from INSTPM

While wandering in the spec, I noticed that BDW removes those 2 bits
from INSTPM. I couldn't find any direct way to invalidate the TLB (ie
without the ring working already). Maybe someone will be more lucky.

At least, we now know we may be a problem.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit dc616b89dbc4bb6a99884d214bd1ed1e0eef59a0)

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: Ic97eddee95e4a62df19ea482f501083e4d99c04f
Reviewed-on: https://chromium-review.googlesource.com/191333
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
Commit-Queue: James Ausmus <james.ausmus@intel.com>
[DO NOT REBASE] drm/i915: Don't clobber CHICKEN_PIPESL_1 on BDW

Misplaced parens cause us to totally clobber the CHICKEN_PIPESL_1
registers with 0xffffffff. Move the parens to the correct place
to avoid this.

In particular this caused bit 30 of said registers to be set, which
caused the sprite CSC to produce incorrect results.

Cc: stable@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72220
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit c7c656226842679bcd9f39dc24441b4ff398a850)

Conflicts:
	drivers/gpu/drm/i915/intel_pm.c

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: I6d961bd0d702b4c7efb2173bbef579b6696f8e1c
Reviewed-on: https://chromium-review.googlesource.com/191334
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
Commit-Queue: James Ausmus <james.ausmus@intel.com>
[DO NOT REBASE] drm/i915: don't flood the logs about bdw semaphores

BDW is no longer flagged as preliminary hw, but without
i915.preliminary_hw_support module param set the logs are filled with
WARNs about it.

Just make semaphores off the BDW per-chip default for now.

CC: Ben Widawsky <ben@bwidawsk.net>
Reported-by: Sebastien Dufour <sebastien.dufour@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit c923facd535b97972b5bb7d3df4fcafd61a63a5e)

Conflicts:
	drivers/gpu/drm/i915/i915_drv.c

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: I47c3492d4f30ea4511caa6b874555fca6639dfd4
Reviewed-on: https://chromium-review.googlesource.com/191335
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
Commit-Queue: James Ausmus <james.ausmus@intel.com>
[DO NOT REBASE] drm/i915/bdw: Use scratch page table for GEN8 PPGTT

I'm not clear if the hardware is still subject to the same prefetching
issues that made us use a scratch page in the first place. In either
case, we're using garbage with the current code (we will end up using
offset 0).

This may be the cause of our current gem_cpu_reloc regression with
PPGTT. I cannot test it at the moment.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 8407bb9129da95fc4099b84cdbbc23e6d4f66aee)

Conflicts:
	drivers/gpu/drm/i915/i915_gem_gtt.c

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: Ib8161b4d6b7926075c66f260df75c38c01a13d41
Reviewed-on: https://chromium-review.googlesource.com/191336
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
Commit-Queue: James Ausmus <james.ausmus@intel.com>
[DO NOT REBASE] drm/i915/bdw: Restore PPAT on thaw

Apparently it is wiped out from under us, and we get some really fun
caching artifacts upon resume (it seems to be WB for all types by
default).

Reported-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: James Ausmus <james.ausmus@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76113
Tested-by: Timo Aaltonen <timo.aaltonen@canonical.com>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit a2319c08bfd849ea32b4f890ce92df86074c5731)

Conflicts:
	drivers/gpu/drm/i915/i915_gem_gtt.c

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: Id12dab77642e3e94e3e63537ee504d32e3258ab4
Reviewed-on: https://chromium-review.googlesource.com/191337
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
Commit-Queue: James Ausmus <james.ausmus@intel.com>
[DO NOT REBASE] drm/i915/bdw: Free PPGTT struct

GEN8 never freed the PPGTT struct. As GEN8 doesn't use full PPGTT, the
leak is small and only found on a module reload. ie. I don't think this
needs to go to stable.

v2: The very naive, kfree in gen8 ppgtt cleanup, is subject to a double
free on PPGTT initialization failure. (Spotted by Imre). Instead this
patch pulls the ppgtt struct freeing out of the cleanup and leaves it to
the allocators/callers or the one doing the last kref_put as in standard
convention

Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit b18b6bde300e1abe30e8b27501411a4b4a95ffeb)

Conflicts:
	drivers/gpu/drm/i915/i915_gem_context.c

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: Ie6806f6897934a3475cc7e96d619cf41d12632d5
Reviewed-on: https://chromium-review.googlesource.com/191338
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
Commit-Queue: James Ausmus <james.ausmus@intel.com>
[DO NOT REBASE] drm/i915/bdw: Split up PPGTT cleanup

This will make the code more readable, and extensible which is needed
for upcoming feature work. Eventually, we'll do the same for init.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit b45a67157a609da83f6b2e6803296c5ccb2f8c8d)

Conflicts:
	drivers/gpu/drm/i915/i915_gem_gtt.c

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: Ib5dc7f3af1c42727ad6231ac51d17041cd325812
Reviewed-on: https://chromium-review.googlesource.com/191339
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
[DO NOT REBASE] drm/i915/bdw: Reorganize PPGTT init

Create 3 clear stages in PPGTT init. This will help with upcoming
changes be more readable. The 3 stages are, allocation, dma mapping, and
writing the P[DT]Es

One nice benefit to the patches is that it makes 2 very clear error
points, allocation, and mapping, and avoids having to do any handling
after writing PTEs (something which was likely buggy before). This
simplified error handling I suspect will be helpful when we move to
deferred/dynamic page table allocation and mapping.

The patches also attempts to break up some of the steps into more
logical reviewable chunks, particularly when we free.

v2: Don't call cleanup on the error path since that takes down the
drm_mm and list entry, which aren't setup at this point.

v3: Fixes addressing Imre's comments from:
<1392821989.19792.13.camel@intelbox>

Don't do dynamic allocation for the page table DMA addresses. I can't
remember why I did it in the first place. This addresses one of Imre's
other issues.

Fix error path leak of page tables.

v4: Fix the fix of the error path leak. Original fix still leaked page
tables. (Imre)

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit f3a964b96d792eac67976a3bb296a0d2049b4f91)

Conflicts:
	drivers/gpu/drm/i915/i915_gem_gtt.c

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: I8601594a0b1bd032ce83ba9cb07d61a382c6e28a
Reviewed-on: https://chromium-review.googlesource.com/191340
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
[DO NOT REBASE] drm/i915/bdw: Split ppgtt initialization up

Like cleanup in an earlier patch, the code becomes much more readable,
and easier to extend if we extract out helper functions for the various
stages of init.

Note that with this patch it becomes really simple, and tempting to begin
using the 'goto out' idiom with explicit free/fini semantics. I've
kept the error path as similar as possible to the cleanup() function to
make sure cleanup is as robust as possible

v2: Remove comment "NB:From here on, ppgtt->base.cleanup() should
function properly"
Update commit message to reflect above

v3: Rebased on top of bugfixes found in the previous patch by Imre
Moved number of pd pages assertion to the proper place (Imre)

v4:
Allocate dma address space for num_pd_pages, not num_pd_entries (Ben)
Don't use gen8_pt_dma_addr after free on error path (Imre)
With new fix from v4 of the previous patch.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit bf2b4ed291a8a3681ba0cb50b6ba5423c47b9fac)

Conflicts:
	drivers/gpu/drm/i915/i915_gem_gtt.c

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: I2e166c44c968e26772dc4f5d051e9343720abf4d
Reviewed-on: https://chromium-review.googlesource.com/191341
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
[DO NOT REBASE] drm/i915: Make clear/insert vfuncs args absolute

This patch converts insert_entries and clear_range, both functions which
are specific to the VM. These functions tend to encapsulate the gen
specific PTE writes. Passing absolute addresses to the insert_entries,
and clear_range will help make the logic clearer within the functions as
to what's going on. Currently, all callers simply do the appropriate
page shift, which IMO, ends up looking weird with an upcoming change for
the gen8 page table allocations.

Up until now, the PPGTT was a funky 2 level page table. GEN8 changes
this to look more like a 3 level page table, and to that extent we need
a significant amount more memory simply for the page tables. To address
this, the allocations will be split up in finer amounts.

v2: Replace size_t with uint64_t (Chris, Imre)

v3: Fix size in gen8_ppgtt_init (Ben)
Fix Size in i915_gem_suspend_gtt_mappings/restore (Imre)

Reviewed-by: Imre Deak <imre.deak@intel.com> (v2)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 782f149523d31a24a54e4abd2db6ce2b2106af8d)

Conflicts:
	drivers/gpu/drm/i915/i915_gem_gtt.c

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: Iba96e59e45e152840ddd01c2139357893193b4f1
Reviewed-on: https://chromium-review.googlesource.com/191342
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
[DO NOT REBASE] drm/i915/bdw: Reorganize PT allocations

The previous allocation mechanism would get 2 contiguous allocations,
one for the page directories, and one for the page tables. As each page
table is 1 page, and there are 512 of these per page directory, this
goes to 2MB. An unfriendly request at best. Worse still, our HW now
supports 4 page directories, and a 2MB allocation is not allowed.

In order to fix this, this patch attempts to split up each page table
allocation into a single, discrete allocation. There is nothing really
fancy about the patch itself, it just has to manage an extra pointer
indirection, and have a fancier bit of logic to free up the pages.

To accommodate some of the added complexity, two new helpers are
introduced to allocate, and free the page table pages.

NOTE: I really wanted to split the way we do allocations, and the way in
which we identify the page table/page directory being used. I found
splitting this functionality up to be too unwieldy. I apologize in
advance to the reviewer. I'd recommend looking at the result, rather
than the diff.

v2/NOTE2: This patch predated commit:
6f1cc993518462ccf039e195fabd47e7aa5bfd13
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Tue Dec 31 15:50:31 2013 +0000

    drm/i915: Avoid dereference past end of page arr

It fixed the same issue as that patch, but because of the limbo state of
PPGTT, Chris patch was merged instead. The excess churn is a result of
my using my original patch, which has my preferred naming. Primarily
act_* is changed to which_*, but it's mostly the same otherwise. I've
kept the convention Chris used for the pte wrap (I had something
slightly different, and broken - but fixable)

v3: Rename which_p[..]e to drop which_ (Chris)
Remove BUG_ON in inner loop (Chris)
Redo the pde/pdpe wrap logic (Chris)

v4: s/1MB/2MB in commit message (Imre)
Plug leaking gen8_pt_pages in both the error path, as well as general
free case (Imre)

v5: Rename leftover "which_" variables (Imre)
Add the pde = 0 wrap that was missed from v3 (Imre)

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Squash in fixup from Ben.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 7ad47cf252d432c8006589fa23de4ed61f1ac30f)

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: Id06f43f8d2fd8feecba4033ec7fb165b17563e37
Reviewed-on: https://chromium-review.googlesource.com/191343
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
[DO NOT REBASE] Revert "drm/i915/bdw: Limit GTT to 2GB"

This reverts commit 3a2ffb65eec6dbda2fd8151894f51c18b42c8d41.

Now that the code is fixed to use smaller allocations, it should be safe
to let the full GGTT be used on BDW.

The testcase for this is anything which uses more than half of the GTT,
thus eclipsing the old limit.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 7907f45bf9f67a1c5e5d4ae05bab428d7c2f43b2)

Conflicts:
	drivers/gpu/drm/i915/i915_gem_gtt.c

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: I456acfabda34636f1ad8d17413534954b5eb78a6
Reviewed-on: https://chromium-review.googlesource.com/191344
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>
[DO NOT REBASE] drm/i915: Don't use i915_preliminary_hw_support to mean pre-production

Those are two distinct concepts. Just use a comment to remind us to
remove that W/A at some point.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 4167e32ce0db0af42b57b93eb8faf28fc094db10)

Conflicts:
	drivers/gpu/drm/i915/intel_pm.c

BUG=none
TEST=Boot and browse on a bwtm2

Change-Id: I189cb7506ec950bf65f3173230f8230566c94617
Reviewed-on: https://chromium-review.googlesource.com/191345
Tested-by: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Ben Zhang <benzh@chromium.org>