ram_wb: Do not check address overruns

Since the module itself has no idea of how the interconnect looks like
it cannot figure out if the address is out of bounds.
Do not plute ram_wb with functions in synthesis

Move the helper functions for Verilator inside the ifdef.
This will make Xilinx Vivado infer block RAMs for the module.
Added module name as argument to wb_intercon_gen

This change allows a user to specify the module name for a wishbone
interconnect. This is useful when you want to have two or more busses in
your design.
move debug signals declaration up

to before they are used in the adbg module
Merge branch 'wb-intercon-name' of github.com:bluecmd/orpsoc-cores into upstream
Merge branch 'fixdeclorder' of github.com:jjts/orpsoc-cores into upstream
Merge branch 'master' of https://github.com/openrisc/orpsoc-cores