Add testNameItTooEager153 for issue #153. This requires more investigation.
Fix for #153 - NameIt is way too eager, needs to chill out (in Verilog-backend only).

Node.nameIt currently applies the '_' disambiguation logic even if a
node hasn't been named yet. Ignore unnamed nodes under the assumption
we will eventually get around to naming them.
Remove debugging code.
Minor change to trigger disambiguation on node name != "".

We may want to add additional logic to support a class of names that
should not be altered. Make the nameIt() disambiguation code simply
avoid trying to disambiguate empty names.
Merge pull request #307 from ucb-bar/nameit153

 Fix for #153 - NameIt is way too eager, needs to chill out (in Verilog-backend only).