arm: dts: exynos542x: Refactor exynos5420 dts files

We are going to add a new variant of exynos5420 series which is almost
similar to exsisting exynos5420 SoC. This is ground work to add support
for new SoC.
In this patch we are just renaming file which will be used as common
file.

BUG=chrome-os-partner:24687
TEST=build and booted on pit, and everything works fine
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>

Change-Id: I65c848e3219dac5d697a7d0003e92f020abeffe4
Reviewed-on: https://chromium-review.googlesource.com/181327
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Commit-Queue: Doug Anderson <dianders@chromium.org>
drm/exynos: Ensure mixer vsync irqs are enabled/disabled properly

This patch does the following:
- Ensures int_en always tracks the desired vsync state
- Clears MXR_INT_EN on power off to avoid the interrupts firing too
  early on poweron when we enable the clocks
- Refrains from enabling vsync until all window state has been restored

All together, this will avoid turning on vsync too early such that we
have inconsistent window state which causes iommu faults. Or, at least
that's the theory.

BUG=chrome-os-partner:24923,chromium:332599,chromium:331138
TEST=tested on daisy - hotplug/suspend-resume/resolution change

Change-Id: Iabeae6240dfd031a407a8517f5f74fc2cf97cdc1
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181987
drm/exynos: add phy settings for rb modes

This patch adds new phy setting for pixel clocks
73.25MHz,88.75MHz, 115.5MHz, and 119MHz which
are used for enabling reduced blanking modes like
1680x1050 etc.

BUG=chrome-os-partner:24846
TEST=connect 1080p monitor to Pit,
verified listing of 1680x1050@119000000

Change-Id: Id3c3f0d36063fa932fcf96af1a12968288d016e8
Signed-off-by: Shirish S <s.shirish@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/182034
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Dominik Behr <dbehr@chromium.org>
CHROMIUM: drm: Refactor drm_bridge to track upstream patch

This patch changes drm_bridge such that it is now statically
associated with an encoder instead of a connector. This requires
the bridge to be connected to the encoder statically on init.

This patch renames prepare to disable and adds new hooks for
post_disable, mode_set, pre_enable, enable which are called from crtc
helper's mode_set function.

Drop this patch in the next version of the kernel in favor of "drm: Add
drm_bridge"

BUG=chromium:266008
TEST=Tested on snow

Change-Id: Ie78cf82253b77d660b04220b3f901a35ca10b41d
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/64778
drm/exynos: Tie bridge initialization directly to encoder creation

Now that bridges are both connector and bridge, we need to tie their
initialization directly into encoder creation. Furthermore, if there is
a bridge for our encoder, we should not create a connector.

BUG=chromium:266008
TEST=Tested on snow with DP

Change-Id: I4e0eb3da13857a78be9dcec507c12e9f7e49370c
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/65786
drm/ptn3460: Refactor ptn3460 driver to match drm_bridge

This patch refactors ptn3460 to match the new drm_bridge interface
and changes it to be both a bridge and a connector. This allows us
a few things:
	- Directly use the EDID emulation via i2c
	- Return an accurate connector type (LVDS) to userspace
	- Always return connected instead of relying on hotplug

BUG=chromium:266008
TEST=Tested on snow

Change-Id: I04d1c9d6d82621fdd058d84a13c0ee0fb2d2119a
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/65785
drm/ps8622: Rename bridge to ps_bridge

BUG=chromium:266008
TEST=Tested on peach pit and spring

Change-Id: I5fc338ec5b5fe397a722b6155463731198c1b36a
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179217
drm/ps8622: Refactor ps8622 driver to match drm_bridge

This patch refactors ps8622 to match the new drm_bridge interface
and changes it to be both a bridge and a connector. This allows us
a few things:
	- Return an accurate connector type (LVDS) to userspace
	- Always return connected instead of relying on hotplug

BUG=chromium:266008
TEST=Tested on peach pit and spring

Change-Id: I677abce5ee623a0b2319c7c82dc27da1bdb08612
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/168061
CHROMIUM: ARM: exynos: Add ps8622 mode info to peach pit

This patch adds the LVDS panel mode information to the ps8622 node for
peach pit.

BUG=chromium:266008
TEST=Tested on peach pit

Change-Id: I2ae1d37fecc143cadddd425b33ee84fc0e446f2e
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/168062
CHROMIUM: ARM: exynos: Add ps8622 mode info to spring

This patch adds the LVDS panel mode information to the ps8622 node for
spring

BUG=chromium:266008
TEST=Tested on spring

Change-Id: Iea4169bb1a4e03070a9b71aed820b786eadff3c0
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/168063
arm: Add Arm Erratum 773769 for Large data RAM latency

The erratum-773769 occurs on ARM Cortex-A15 (rev r2p0 or earlier) when
effective L2 Data RAM latency is set to 4 cycles or more, or when ACP
is in use, or with L2 Data RAM slice configured.  Therefore, the
effective latency as calculated in Table 7-2 of Cortex-A15 (rev r2p0)
TRM should be 3 cycles or less.

With our current setup on exynos5250 systems the effective
data ram latency is 4 cycles, since we have
DATA_RAM_SETUP bit enabled (L2CTRL[5]=1b'1) and
DATA_RAM_LATENCY bits set to 2 (L2CTLR[2:0]=3b'010) therefore,
the effective L2 data RAM latency becomes 4 cycles.
So erratum '773769' occurs causing a corrupted L2 Cache.

This patch gives a workaround to the mentioned erratum, using below
mentioned algo:
----------------------------------------------------------------
if DATA_RAM_LATENCY >= 0x2)
	DATA_RAM_SETUP = 0
if (DATA_RAM_LATENCY > 0x2)
	DATA_RAM_LATENCY = 0x2
----------------------------------------------------------------
so that the effective data RAM latency reduces to 3 cycles or less
and hence prevent hitting the erratum.

This patch is posted upstream at:
  https://patchwork.kernel.org/patch/3453631/

BUG=chrome-os-partner:21370,chrome-os-partner:24306
TEST=Run Google texture upload test after a suspend/resume
     cycle on Lucas ve boards.

Change-Id: Ibc9fd38a66daebf0d33a6f63e30ccf150030e0c3
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180577
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
CHROMIUM: mfd: cros_ec: Create sysfs attributes for the ChromeOS EC.

This adds the first few sysfs attributes for the Chrome OS EC. These
controls are made available under /sys/devices/virtual/chromeos/cros_ec

  flashinfo   - display current flash info
  reboot      - tell the EC to reboot in various ways
  version     - information about the EC software and hardware

Future changes will build on this to add additional controls.

BUG=chromium:239205
TEST=manual for now, autotest coming soon (crbug.com/334014)

From a root shell, you should be able to do things like this:

  cd /sys/devices/virtual/chromeos/cros_ec
  cat flashinfo
  cat version
  echo rw > reboot
  cat version
  echo ro > reboot
  cat version
  echo rw > reboot
  cat version
  echo cold > reboot

That last command will reboot the AP too.

Change-Id: I4b16245b855b6a71baa1f9001ef484f6a6115d4f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176840
Reviewed-by: Olof Johansson <olofj@chromium.org>
ARM: EXYNOS: Change the base address values for zreladdr-y,params_phys-y
from 40000000 to 20000000

This patch is temporarily to boot.
i2c: exynos5: Clock_disable_unprepare comment temporarily
ARM: Add Kconfig to 16 of NR_BANKS for EXYNOS5420
ARM: dts: Add Initial device tree support for odroidxu2

Add initial device tree for odroidxu2
ARM: odroidxu2_defconfig: odroidxu2 board based on exynos5420
 ARM: dts: odroid-xu2: Add heartbead and mmc LEDs support

 Add the support for LED1 on ODROID-XU2 board.
 -Blue LED will be used for heartbeat
 -Green LED will be used for eMMC
 -Red LED will be used for microSD
ARM: odroidxu2_defconfig: Disable CONFIG_SECURITY_CHROMIUMOS
ARM: dts: Add dp_hpd properties for DP on odroid-xu2