b200: Moved AD9361 driver to host

- Switched to FPGA SPI engine
- Moved firmware AD9361 driver to UHD
- Bumped FW compat to 5, FPGA compat to 4
- Known Issue: AD9361 SPI rate is too slow
b200: AD9361 firmware bugfixes

- Fix for BUG #485:  B200: Channels Swap Between Runs
  # Added code to transition state machine out of FDD while reconfiguring active chains.
  # bb:0b9929 Mon Jun 16 14:56:26 2014 -0700

- Fix for BUG #500:  B210: RX channels are not phase aligned
  # Set bit to invert RX if internal LNA is bypassed
  # bb:0a4565 Thu Jun 5 17:10:37 2014 -0700
b200: Added variable rate SPI core for AD9361 and ADF4001

- Added b200_local_spi core that adjusts the divider when talking to the two chips
- AD9361 rate is 1MHz and ADF4001 rate is 10kHz
Merge branch 'master' into ashish/cat_refactor_master
octoclock: Fixed merge conflict. Utils compile now.
Merge remote-tracking branch 'origin/master' into ashish/cat_refactor_master
docs: adding page for NIRIO kernel driver install, linking to it
docs: fixing broken doxygen syntax in some existing docs
b200: Removed all AD9361 related firmware

- FX3 does not respond to AD9361 firmware transaction VREQs
- FX3 does not respond to AD9361 SPI transaction VREQs
- Deleted all AD9361 firmware files
- Bumped FW compat to 6
b200, ad9361: Cleanup up AD9361 driver

- Removed transaction interface
- Made the driver a C++ class
ad9361: Renamed ad9361_impl.c to ad9361_device.cpp
ad9361: Converted stdint types to boost types
ad9361: Cleaned up errors and debug messages
Merge remote-tracking branch 'origin/master' into ashish/cat_refactor_phase2
ad9361: Cleaned up constants and macros
ad9361: Added synchronization to IO and device classes
ad9361: Fixed TX direction bug in ad9361_ctrl
ad9361: Fixed debug messages with UHD_LOGs
ad9361: Fixed MSVC build issues
Merge branch 'maint'