Bug 328100 - XABORT not implemented.

XABORT can be called even when there is no current transaction.
In such a case XABORT acts as a NOP. Implement xabort as nop.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2800 8f6e269a-dfd6-0310-a8e1-e2731360e62c
The result of rounding a 128-bit BFP/DFP value to 32/64 bit needs to
be stored in a register pair. This constraint was not observed previously
and the result was stored in any FPR that happened to be chosen. If the
selected FPR was not identifying a proper FPR pair, a SIGILL was delivered.
Fixes BZ #328455.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2801 8f6e269a-dfd6-0310-a8e1-e2731360e62c
LibVEX_GuestAMD64_initialise(): give an initial value for
guest_ACFLAG.  Kinda worrying that this was missing.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2802 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add support for ARMv8 AArch64 (the 64 bit ARM instruction set):
integer and FP instructions.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2803 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add missing ULLs to some 64-bit immediates.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2804 8f6e269a-dfd6-0310-a8e1-e2731360e62c
arm64: rename guest_SP to guest_XSP so as to avoid a name clash with
guest_SP from s390 world.  Also back out the rename of guest_SP to
guest_s390_SP that caused s390 build breakage in r2803.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2805 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips64: Change the initial value of fpu registers.

Initial value of mips fpu registers should be nan instead of 0xffffffffffffffff.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2806 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Whitespace-only change: restrict to 80 col width.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2807 8f6e269a-dfd6-0310-a8e1-e2731360e62c
This patch by adrian.sendroiu@freescale.com fixes the lrmw and stmw
instructions.

The patch also adds ppc32 and ppc64 test cases for the instructions.

The patch is a fix for bugzilla 329956 "valgrind crashes when lmw/stmw instructions are used on ppc64".



git-svn-id: svn://svn.valgrind.org/vex/trunk@2808 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Make the following primops take a third (initial) argument to
indicate the rounding mode to use, like their scalar cousins do:

  Iop_Add32Fx4  Iop_Sub32Fx4  Iop_Mul32Fx4  Iop_Div32Fx4  
  Iop_Add64Fx2  Iop_Sub64Fx2  Iop_Mul64Fx2  Iop_Div64Fx2  
  Iop_Add64Fx4  Iop_Sub64Fx4  Iop_Mul64Fx4  Iop_Div64Fx4
  Iop_Add32Fx8  Iop_Sub32Fx8  Iop_Mul32Fx8  Iop_Div32Fx8

Fix up the x86 and amd64 front ends to add fake rounding modes
(Irrm_NEAREST) when generating expressions using these primops.
Fix up the x86 and amd64 back ends to accept these as triops
rather than as binops, and ignore the first arg.

Add three more ir_opt folding rules to remove memcheck
instrumentation arising from instrumentation of known-defined
rounding modes.

Overall functional and performance effects should be zero.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2809 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Improve front and back end support for SIMD instructions on Arm64.

Implement the following instructions -- some but not necessarily
all laneage combinations:

  LD1 {vT.2d},  [Xn|SP]
  ST1 {vT.2d},  [Xn|SP]
  LD1 {vT.4s},  [Xn|SP]
  ST1 {vT.4s},  [Xn|SP]
  LD1 {vT.8h},  [Xn|SP]
  ST1 {vT.8h},  [Xn|SP]
  LD1 {vT.16b}, [Xn|SP]
  ST1 {vT.16b}, [Xn|SP]
  LD1 {vT.1d}, [Xn|SP]
  ST1 {vT.1d}, [Xn|SP]
  LD1 {vT.2s}, [Xn|SP]
  ST1 {vT.2s}, [Xn|SP]
  LD1 {vT.4h}, [Xn|SP]
  ST1 {vT.4h}, [Xn|SP]
  LD1 {vT.8b}, [Xn|SP]
  ST1 {vT.8b}, [Xn|SP]
  ST1 {vT.2d}, [xN|SP], #16
  LD1 {vT.2d}, [xN|SP], #16
  ST1 {vT.4s}, [xN|SP], #16
  ST1 {vT.8h}, [xN|SP], #16
  ST1 {vT.2s}, [xN|SP], #8
  SCVTF Vd, Vn
  UCVTF Vd, Vn
  FADD Vd,Vn,Vm   1
  FSUB Vd,Vn,Vm   2
  FMUL Vd,Vn,Vm   3
  FDIV Vd,Vn,Vm   4
  FMLA Vd,Vn,Vm   5
  FMLS Vd,Vn,Vm   6
  ADD Vd.T, Vn.T, Vm.T
  SUB Vd.T, Vn.T, Vm.T
  XTN {,2}
  DUP Vd.T, Vn.Ts[index]



git-svn-id: svn://svn.valgrind.org/vex/trunk@2810 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips64: Support for Cavium-specific load indexed instructions

Support for lhux, lwux, lbx for Cavium.

Patch by Zahid Anwar, with style changes.

Related to Bugzilla issue 326444.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2811 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Implement a few more vector aarch64 insns:
LD1 {vT.4s}, [xN|SP], #16
ADD Dd, Dn, Dm
SUB Dd, Dn, Dm
SMIN Vd.T, Vn.T, Vm.T
UMIN Vd.T, Vn.T, Vm.T
SMAX Vd.T, Vn.T, Vm.T
UMAX Vd.T, Vn.T, Vm.T
SMINV Vd.T, Vn.T, Vm.T
UMINV Vd.T, Vn.T, Vm.T
SMAXV Vd.T, Vn.T, Vm.T
UMAXV Vd.T, Vn.T, Vm.T
DUP Vd.T, Rn
FADD/FSUB/FMUL/FDIV32x4



git-svn-id: svn://svn.valgrind.org/vex/trunk@2812 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Implement a few more vector aarch64 insns:
LD1 {vT.8h}, [xN|SP], #16
LD1 {vT.16b}, [xN|SP], #16
ST1 {vT.4h}, [xN|SP], #8
MUL  Vd.T, Vn.T, Vm.T
PMUL Vd.T, Vn.T, Vm.T  (fe only)
MLA  Vd.T, Vn.T, Vm.T
MLS  Vd.T, Vn.T, Vm.T
UMOV Xd/Wd, Vn.Ts[index]
SMOV Xd/Wd, Vn.Ts[index]



git-svn-id: svn://svn.valgrind.org/vex/trunk@2813 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add support for syscall on x86

Patch from Ivo Raisr via BZ#330939 also fixes BZ#308729


git-svn-id: svn://svn.valgrind.org/vex/trunk@2814 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Implement more aarch64 vector insns:
{S,U}{MIN,MAX}  Vd.T, Vn.T, Vm.T (8bitx16lane variants)
{S,U}{MIN,MAX}V Vd.T, Vn.T, Vm.T (8bitx16lane variants)
FMOV (vector, immediate)
MOVI (vector, immediate)
FABS (vector)
FNEG (vector)
FMLA (vector)
FMLS (vector)
{AND,BIC,ORR,ORN} (vector)



git-svn-id: svn://svn.valgrind.org/vex/trunk@2815 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Fix the ppc32 special-instruction magic sequence so it really does
preserve the value of r0, as claimed.  Fixes #278808 (VEX side).


git-svn-id: svn://svn.valgrind.org/vex/trunk@2816 8f6e269a-dfd6-0310-a8e1-e2731360e62c
s390: Fix s390_amode_for_guest_state. In general the offset relative 
to the guest state pointer may be more than the B12 addressing mode can
handle. Fall back and use a B20 addressing mode in those cases.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2817 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Fix comments and code snippets that were making incorrect claims about
the alignment requirement of the guest state, shadow areas, and register
spill area sizes.
The size of these areas ought to be a multiple of 16 bytes.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2818 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips64: add support for load indexed instructions from DSP ASE

Handling lwx, ldx and lbux for MIPS-Cavium processors.

Patch by Zahid Anwar, with some changes.

Related to Bugzilla issue 326444.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2819 8f6e269a-dfd6-0310-a8e1-e2731360e62c