msm: msm_bus: Correct the return value from register-client

On failure, return 0, and not a non-zero value as that can
be interpreted as a valid client ID.

Change-Id: I7a5b448bc398b4a4792170147a5e5317d25f8b3c
CRs-Fixed: 486328
Signed-off-by: Gagan Mac <gmac@codeaurora.org>
msm: subsystem_restart: Change the error ready log message

The error services interrupt log message appears as if it is
reporting an error. So, change it so that it does not appear so.

Change-Id: I84049af9d369d1c87547225813ec6cf1c4a66db5
Signed-off-by: Seemanta Dutta <seemanta@codeaurora.org>
msm: clock-generic: Handle round rate return values greater than LONG_MAX

The return type of clk_round_rate() is long. So, technically it can return
only rates as large as LONG_MAX (~2.1 GHz). But CPU clocks can already go
past 2.1 GHz and any return value greater than LONG_MAX will appear as a
negative number to the caller.

So, make the clock-generic implementation a bit more selective/intelligent
about treating negative return values from clk_round_rate() as errors. If
the returned negative number is not one of the standard error values
(IS_ERR_VALUE), then treat the negative long number as an unsigned long
rate.

Change-Id: I27383bdb74ed6986667fee681005adec7b16bde9
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-8610: Correct bimc_clk measurement mux select

The bimc_clk measurement mux select value is wrong.
Fix it so that the right clock is measured.

CRs-Fixed: 495360
Change-Id: I3230817fb9f5851d0c98a52338e8cb74a3e2cef4
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm: clock-8974: Support 8974ac frequency plan

Update frequency tables and fmax settings for certain
clocks to match the latest 8974ac frequency plan data.

Change-Id: Iad9d7485eeae0c9f21f5829a96fab355fa575bd2
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: clock-rpm: Correct is_enabled implementation for RPM-SMD clocks

Clocks using the RPM-SMD driver have no way to query
clock state from the RPM. Therefore do not use the
get_rate function to figure out the enable-state of
the clock.

Change-Id: I4d142c716a4e41e54185e4ed4fe9feb33a1c2427
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm: acpuclock-cortex: Select freq plan based on speed bin value

Due to process variation, not all hw has the same max speed. Duplicate
each speed_bin twice to allow greater flexibility between process yield
and chip demand. The bin values are chosen so that additional fuses can be
blown once to change between bins without the use of the multipurpose
redundant fuses.

Change-Id: I2e4f8c5c4d29e0461b455a3bd46a884bb43f6c20
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
msm: krait-regulator: enable support for KPSS v2 hardware

KPSS version 2.1 introduces a hardware sequencer which executes
the necessary steps to switch between BHS and LDO krait power modes.
The driver has to set the APC_PWR_GATE_MODE register to initiate a
switch between LDO and BHS Krait power modes. Modify the driver to
use this hardware sequencer.

Also, switch to the V2 SPM sequence with the delays added for
HW sequencer to idle.

Also, with the V2 sequences, it is expected that APC_PWR_GATE_CTL
register be configured once before using the APC_PWR_GATE_MODE register to
switch between LDO and BHS.

Update the code such that for secondary cpus APC_PWR_GATE_MODE is
written to after configuring APC_PWR_GATE_CTL in the
secondary_cpu_hs_init() function. Note that secondary_cpu_hs_init() is
guaranteed to run only once for each secondary cpu when that core is
brought up for the first time. Subsequent hotplug in/out of that core
do not take this code execution path.

For boot cpu, since it is up and running, its APC_PWR_GATE_CTL
should already be initialized. So for boot cpu configure its
APC_PWR_GATE_MODE register right at probe time. secondary_cpu_hs_init()
isn't invoked for boot cpu.

Change-Id: Ie5584c12f47283cad8834ccdb3d4d44c66305a22
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
msm: clock-8974: Fix 8974ac gpll4 and mclk changes

GPLL4 only exists on v3 variants, and shouldn't be in the lookup table
for v1/v2.  Camera MCLK is changed to match its clock type.

Change-Id: Id15313bfcaed783f7f835ff75f651e38d4bad8de
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: acpuclock-8974: Add support for 8974v3 speed bin

Add v3 frequency and voltage data corresponding to the voltage plan
for bringup.

Change-Id: I02f8885a5bc7798c5cfcae34cf952675f346b208
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: clock: Add a CXO voter for the LPM driver

The Low Power Mode resources driver needs to vote for
CXO in certain conditions. Add a voter clock for that
driver to the 9625/8226/8610 clock drivers.

Also, while we're here, create voter clocks for CXO
wherever necessary.

Change-Id: I07c9aed2ab67a58d296041a62049de63277995cd
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm: pm-8x60: Update the identity mapping for LPAE

The pm code uses a known stable page table with an identity mapping
for coming in and out of power collapse. This table currently assumes
a standard two level page table. This is incompatible with the new
format for LPAE. Update the code to handle both the LPAE and non-LPAE
page tables for power collapse.

Change-Id: I58097744134207fac49d7ab2147ba34f2f244a94
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
msm: acpuclock-8974: Apply 8974Pro bringup workaround

Fix soc version detection for 8974Pro and force 8974ab to use bringup
voltage plan.

Change-Id: I84bc7bf0912223b3826b8420c19c9e93e6a9f816
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: clock-8974: Add support for 8974Pro aa/ab/ac variants

8974Pro aa/ab/ac have different Camera and SDCC frequencies.
Update them to match the latest clock plan.  In addition,
enable aux output of MPLL3 for Camera VFE.

Change-Id: I00835242719717de0c51f694b6976c8fe00418f1
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: clock-generic: Make ops options for div_clk

Fixed divider clocks have no need for any clk_div_ops. So, make the entire
ops optional for div_clk. With this in mind, add more NULL pointer checks
for ops.

Change-Id: Ic5e2069a9a3c2c2cadf9285e1f1b9774cc5bf8f9
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-pll: Add clk_round/set_rate() support for fixed rate PLLs

For any clock that dynamically decides the right parent to use during a
clk_set_rate() call, the parents need to support clk_round_rate() and
clk_set_rate() APIs to aid with the decision making. Since PLLs could be
parents to such clocks, add support for these clk_set_rate() and
clk_round_rate() to fixed rate PLLs.

clk_round_rate() always returns the fixed rate of the PLL and
clk_set_rate() fails for any rate that's not equal to the fixed rate of the
PLL.

Change-Id: I867e253040bd9d01f9a8a8437adf511553bfcbfe
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock: Add pre_set_rate and post_set_rate ops

Some clocks might need to perform additional steps before/after a voltage
changes happen during a rate change. To accomodate such clocks and similar
requirements from new clock types in the future, add generic
pre/post_set_rate ops that are called before any HW state change is done
for set rate.

Change-Id: I07e4f79136028aaae5dee6d66d18b45c445f325b
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-mdss: Toggle lock detect before checking for PLL lock

The enable sequences for the DSI PLL for MSM8226 poll a hardware
status register in order to determine whether the PLL has locked.
However, with the current sequences, it is possible that the
hardware status register would indicate a PLL lock even though the
PLL is not really locked. To avoid this, toggle the lock detect
register setting before polling for PLL lock status.

CRs-Fixed: 490476
Change-Id: I6e1357afaa6a86be9ab92095a41768873c70cf0d
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
msm: clock-generic: Fix race condition between mux set rate and en/dis

Some mux implementations might switch to/from a low power parent as part of
their disable/enable ops. This can race with the temporary switch to the
"safe parent" that's done during a mux set rate. So, grab the enable lock
while temporarily switching to the safe parent.

The onus of remembering the last requested set_mux_sel and setting it back
to that when the mux is enabled is still the responsibility of the specific
implementation.

Change-Id: I9ead3334b29ce7d219415cef562424d6455a348d
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm:pm-8x60: Do not generate access flag faults for the kernel mappings

The pgd mapping (msm_pm_pc_pgd) generates Access flag fault whenever
this entry is read into the TLB for the first time. Add this flag to
the pgd mapping such that when the fault occurs, software resets the
Access flag to 1 in the translation table entry that caused the fault.
This prevents the fault from occurring the next time that memory
location is accessed.

Change-Id: I8d2ecc4d4005955ddeeaf3953ca1c445163b694c
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>