docs: remove some ancient README.* files

None of this info is relevant anymore.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
glsl: Extract function for record comparisons.

Reviewed-by: Matt Turner <mattst88@gmail.com>
glsl: Match unnamed record types across stages.

Unnamed record types are assigned to separate types per stage, e.g. if

uniform struct { ... } a;

is defined in both vertex and fragment shader, two separate types will
result with different names. When linking the shader, this results in a
type conflict. However, there is no reason why this should not be
allowed according to GLSL specifications. Compare and match record types
when linking shader stages to avoid this conflict.

Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Print reg_offset for vgrf of size > 1 in dump_instruction().

Previously we wouldn't print the +0 for the first part of a VGRF of size
greater than 1.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/fs: Fix the example about overwriting uniforms in SIMD16.

mov takes only a single source argument. Example instruction
inexplicably changed from add to mov in commit f10f5e49.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
mesa: Add STRINGIFY macro.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/fs: Add and use MAX_SAMPLER_MESSAGE_SIZE definition.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/fs: Add a comment explaining how register coalescing works.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/fs: Assert that var < num_vars.

Helped to track down a problem in a version of the next commit.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/fs: Support coalescing registers of size > 1.

total instructions in shared programs: 1550048 -> 1549880 (-0.01%)
instructions in affected programs:     1896 -> 1728 (-8.86%)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/fs: Calculate interference better in register_coalesce.

Previously we simply considered two registers whose live ranges
overlapped to interfere. Cases such as

   set A     ------
   ...             |
   mov B, A  --    |
   ...         | B | A
   use B     --    |
   ...             |
   use A     ------

would be considered to interfere, even though B is an unmodified copy of
A whose live range fit wholly inside that of A.

If no writes to A or B occur between the mov B, A and the use of B then
we can safely coalesce them.

Instead of removing MOV instructions, we make them NOPs and remove them
at once after the main pass is finished in order to avoid recomputing
live intervals (which are needed to perform the previous step).

total instructions in shared programs: 1543768 -> 1513077 (-1.99%)
instructions in affected programs:     951563 -> 920872 (-3.23%)
GAINED:                                46
LOST:                                  22

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/fs: Call opt_peephole_sel later in the optimization loop.

Calling it after value numbering (added in the next commit) prevents
some instruction count regressions.

total instructions in shared programs: 1524387 -> 1523905 (-0.03%)
instructions in affected programs:     13112 -> 12630 (-3.68%)
GAINED:                                0
LOST:                                  3

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965: Compute the number of live registers at each IP.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965/fs: Show register pressure in dump_instructions() output.

Dumping the number of live registers at each IP allows us to see
register pressure and identify any local maxima.  This should
aid in debugging passes designed to reduce register pressure, as
well as optimizations that suddenly trigger spilling.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/fs: Print the maximum register pressure.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
mesa: rename PreferDP4 to OptimizeForAOS.

This flag was really just a proxy for determining whether the backend
was vector (AOS) or scalar (SOA). It will be used to apply a future
optimization only for vector backends.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
glsl: Add parameter to .equals() to ignore an IR type.

Only implemented for ir_swizzles currently, but perhaps will be useful
for other IR types in the future.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
glsl: Vectorize multiple scalar assignments

Reduces vertex shader instruction counts in DOTA2 by 6.42%, L4D2 by
4.61%, and CS:GO by 5.71%.

total instructions in shared programs: 1500153 -> 1498191 (-0.13%)
instructions in affected programs:     59919 -> 57957 (-3.27%)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
i965: Enable AOS optimizations for the geometry shader.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
glsl: Optimize open-coded lrp into lrp.

total instructions in shared programs: 1498191 -> 1487051 (-0.74%)
instructions in affected programs:     669388 -> 658248 (-1.66%)
GAINED:                                1
LOST:                                  0

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>