First steps towards split clock mode.
Split clock test working so far.  Increments hex display, passes timing.
SDRAM passes basic sanity check
Some more tidying up.
Fixed Dhrystone time calculation, now assumes 60HZ vblank refresh.
Now avoids a wait state for CPU's decode phase.
SDRAM access moved to a faster State Machine. Speed penalty is now about 0.15 DMIPS.
Achieved completely clean timing report and still getting 3.6 DMIPS.
Moved more logic to fast clock, now very slightly outperforms pure 100MHz version.
Ported split clock variant to C3Board.
Added EMS11_bb21 project files.
Added missing firmware files.
Removed extraneous project directories.  HelloWorld DE1 builds again.