Added systemverilog mode

Hi,

I added a mode for SystemVerilog.  It does syntax highlighting and auto indentation.  It's being used already at edaplayground.com.

This could potentially make the existing Verilog mode (which does not do indentation properly) obsolete though the set of keywords are slightly different between the two languages, so I left the Verilog mode as-is.  Also I wasn't sure of the protocol for removing or replacing a mode.

Regards,
-Doug