drivers: bus: omap_l3: Change pr_crit() to dev_err() when IRQ request fails

Use dev_err() which will going to print the driver's name as well and the
KERN_ERR level is sufficient in this case (we also print via dev_err when
there is an error with the mem resources)

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
bus: omap_l3_noc: Fix copyright information

This is an embarrassing patch :(.

Texas Corporation does not make OMAP. Texas Instruments Inc does.

For that matter I dont seem to be able to find a Texas Corporation on
the internet either.

While at it, update coverage to the current year and update the template
to remove redundant information and use the standard boiler plate
licensing.

Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: switched over to relaxed variants of readl/writel

Currently we use __raw_readl and writel in this driver, however, there
is no strict sequencing needs for this driver, hence we should be good
with the relaxed variants.

While at it, simplify address computation using variables for register.

Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: un-obfuscate l3_targ address computation

just simplify derefencing that is equivalent.

Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: move L3 master data structure out

Move the L3 master structure out of the static definition to enable
reuse for other SoCs.

Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: convert target information into a structure

Currently the target instance information is organized indexed by bit
field offset into multiple arrays.

1. We currently have offsets specific to each target associated with each
clock domains are in seperate arrays:

l3_targ_inst_clk1
l3_targ_inst_clk2
l3_targ_inst_clk3

2. Then they are organized per master index in l3_targ.

3. We have names in l3_targ_inst_name as an array to array of strings
corresponding to the above with offsets.

Simplify the same by defining a structure for information containing
both target offset and name. this is then stored in arrays per domain
and organized into an array indexed off domain.

The array is still indexed based on bit field offset.

Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: make error reporting and handling common.

The logic between handling CUSTOM_ERROR and STANDARD_ERROR
is just the reporting style.

So make it generic, simplify and standardize the reporting
with both master and target information printed to log.

While at it, fix a minor formatting error.

Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: populate l3->dev and use it

l3->dev is not populated, so populate it and use it to print information
relevant to the device instead of using a generic pr_*.

Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: Add support for discountinous flag mux input numbers

On DRA7, unlike on OMAP4 and OMAP5, the flag mux input numbers used
to indicate the source of errors are not continous. Have a way in the
driver to catch these and WARN the user of the flag mux input thats
either undocumented or wrong.

In the similar vein, Timeout errors in AM43x can't be cleared per h/w
team, neither does it have a STDERRLOG_MAIN to clear the error.

Further, the mux bit offset might not even be indexed into our array
of known mux input description, in which case we'd have a abort.

So, define a static range check for bit description and any definition
which has target_name set to NULL (the ones that are not populated or
ones that are specifically marked in the case of discontinous input
numbers), can handle the same gracefully. Upon occurance of error from
such sources, mask it. Otherwise, we'd have an infinite interrupt
source without any means to clear it.

[nm@ti.com: rebase, squash and improve]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: rename functions and data to omap_l3

Since omap_l3_noc driver is now being used for OMAP5 and reusable with
DRA7 and AM437x, using omap4 specific naming is misleading.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: remove iclk from omap_l3 struct

we do not use iclk directly anymore. And, even if we had to, we
should be using pm_runtime APIs to do the same to be completely SoC
independent.

Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: use of_match_data to pick up SoC information

DRA7xx SoC has the same l3-noc interconnect ip (as OMAP4 and OMAP5), but
AM437x SoC has just 2 modules instead of 3 which other SoCs have.

So, stop using direct access of array indices and use of->match data and
simplify implementation to benefit future usage.

While at it, rename a few very generic variables to make them omap
specific. This helps us differentiate from DRA7 and AM43xx data in the
future.

NOTE: None of the platforms that use omap_l3_noc are non-device tree
anymore. So, it is safe to assume OF match here.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: split, refactor and optimize logic]
Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: convert flagmux information into a structure

This allows us to encompass target information and flag mux offset that
points to the target information into a singular structure. This saves
us the need to look up two different arrays indexed by module ID for
information.

This allows us to reduce the static target information allocation to
just the ones that are documented.

Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: introduce concept of submodule

While OMAP4 and OMAP5 had 3 separate clock domains, DRA7 has only 2
and the first one then is internally divided into 2 sub clock domains.

To better represent this in the driver, we use the concept of submodule.

The address defintions in the devicetree is as per the high level
clock domain(module) base, the sub clockdomain/subdomain which shares
the same register space of a clockdomain is marked in the SoC data as
L3_BASE_IS_SUBMODULE.

L3_BASE_IS_SUBMODULE is used as an indication that it's base address is
the same as the parent module and offsets are considered from the same
base address as they are usually intermingled.

Other than the base address, the submodule is same as a module as it is
functionally so.

Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: Add DRA7 interconnect error data

DRA7 is distinctly different from OMAP4 in terms of masters and clock
domain organization. There two main clock domains which is divided as
follows:
     <0x44000000 0x1000000> is clk1 and clk2 is the sub clock domain
     <0x45000000 0x1000> is clk3

Add all the data needed to handle L3 error handling on DRA7 devices
and mark clk2 as subdomain and provide a compatible flag for
functionality. Other than the data difference the hardware blocks
involved are essentially the same.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: bugfixes and generic improvements, documentation]
Signed-off-by: Nishanth Menon <nm@ti.com>
bus: omap_l3_noc: Add AM4372 interconnect error data

Add AM4372 information to handle L3 error.

AM4372 has two clk domains 100f and 200s. Provide flagmux and data
associated with it.

NOTE: Timeout doesn't have STDERRLOG_MAIN register. And per hardware
team, L3 timeout error cannot be cleared the normal way (by setting
bit 31 in STDERRLOG_MAIN), instead it may be required to do system
reset. L3 error handler can't help in such scenarios.

Hence indicate timeout target offset as L3_TARGET_NOT_SUPPORTED as
done for undocumented bits.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>