Caches: Rename index->tag

The index points to the offset in the cache and tag memory. The tag is
the part left of the index in the address and it is stored in the tag
memory at the addressed index, not the index is stored in the tag.

Some beautification and documentation
Caches: Optimized LRU unit

This is the generic LRU unit. It uses an optimized vector which is of
size (NUMWAYS*(NUMWAYS-1))>>1. The content of the vector is the
reduced set of direct comparisons (x<y) where x is older than y. As
the module forbids x is equally old as y we have a symmetric behaviour
(x<y)=!(y<x).

For four ways the vector is then:

history [5:0] = {(2<3),(1<3),(1<2),(0<3),(0<2),(0<1)}

Further details, the instantiation and the algorithm itself are
documented in the module.
Merge remote-tracking branch 'official/master'
Caches: Support multiple ways

Adds support for more than two ways. The memories are accordingly
replicated, the status vector extended, and some extra multiplexing
added. The caches still use LRU and utilize the optimized LRU unit.
Multicore: Add core identifier

The core identifier can be read from SPR group 0 (system) at address
128 (newly assigned). Furthermore it is possible to read the number of
processor cores in a cluster via register 129. Both can apparently not
be written.

The registers are set via ports, which allow easier use in verilated
models or similar.
Merge branch 'master' into multicore
Merge remote-tracking branch 'openrisc/master' into multicore
WIP: add support for l.lwa/l.swa atomic instructions
cappucino-ctrl: Add two ISRs in multicore mode

We need something like shadow registers in multicore mode as we need
to do clean calculations on exceptions. Add two ISRs (ISR0 and ISR1)
which are used as scratch registers on exceptions.
Debug: Execution traceport

The execution traceport traces all executed program counters, the
respective instruction and accesses to the register file with this
instruction. A rudimentary set of trace actions can be implemented in
a synthesizable way.

Set FEATURE_TRACEPORT_EXEC="ENABLED" to enable this trace port.

Add monitor for simulation.
WIP: Add snoop port
add some more writeable ISR regs

This should be sorted out.
I think the best way to get scratch regs would be to
make a hybrid of the fast context switching and allow
using sets of GPRs (i.e. set 1 for reg stash)
Merge branch 'master' of git://github.com/openrisc/mor1kx into multicore

Conflicts:
	rtl/verilog/mor1kx_cpu_cappuccino.v
	rtl/verilog/mor1kx_ctrl_cappuccino.v
	rtl/verilog/mor1kx_lsu_cappuccino.v
cfgrs: set Architeture Version Reg to 1.1-rev0
cappuccino/fetch: prevent burst signal on regular bus accesses

The ic_refill signal can go high slightly before a regular bus
access have finished.
The burst signal out to the bus interface has to be held off
until the regular bus access is done.
Merge branch 'master' of git://github.com/openrisc/mor1kx into multicore
cappuccino: check atomic_reserve at end of storebuffer

Since there might be a snooped access while the atomic store
(l.swa) is in the storebuffer, the atomic_reserve flag has to
be checked right when the l.swa is coming out from the
store buffer and let out on the bus.

This achieves this by stalling the pipeline while the
l.swa is in the store buffer.

There are a couple of reasons why the atomic goes through
the store buffer and not bypass it.
1) It simplifies some of the logic (less special cases)
2) The store buffer should have knowledge about atomic stores
   going through it, since it place restrictions on what kind
   of re-ordering can be done.
   The current simple store buffer does no such things,
   but this way we are a little more future-proof.
Correct handling of FEATURE_MULTICORE