mmc: tegra: support Tegra124

Tegra124's MMC controller is very similar to earlier SoC generations,
and can be supported by the same driver.

However, there are some non-backwards-compatible HW differences, and
hence a new DT compatible value must be used to describe the HW. This
patch updates the driver to support that new compatible value.

That said, the HW differences are only relevant when enabling certain
high-performance transfer modes. Since the driver is currently very
simple and doesn't enable those modes, we don't actually need to address
any of these HW differences in the code yet, hence the simple nature of
this patch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
---
v2: New patch.

This patch is needed for MMC support on Tegra124 at run-time, but not
strictly required at compile-time. So, it can either go into the MMC
tree and all get merged together in the main U-Boot repo, or the MMC
maintainer can ack it to go through the Tegra tree with the rest of
the changes.
ARM: tegra: misc cleanups triggered by Tegra124 review

Use a named constant for the PLL lock bit in enable_cpu_clocks().

Construct the complete value of pmc_pwrgate_toggle, rather than doing a
read-modify-write; the register is simple enough and doesn't need to
maintain state between operations.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: New patch, split out from the later Tegra124 changes.
ARM: tegra: enable PLLX only once it's been fully configured

This programming sequence is correct per Jimmy Zhang, and makes sense
too!

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: New patch, split out from the later Tegra124 changes.
ARM: tegra: remove a conditional for CSITE rate

There's already an SoC-specific conditional in cpu.h to determine the
PLLP rate. Define the CSITE clock rate inside the same conditional, so
that we can remove a conditional from clock_enable_coresight(). This
means one less place to update the code for new SoCs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: New patch, split out from the later Tegra124 changes.
ARM: tegra: only build __pinmux_nand() when it's needed

__pinmux_nand() won't compile if PERIPH_ID_NDFLASH isn't defined.
Prevent this from causing build problems on newer SoCs without NAND
support (or without SW support for NAND yet), but preventing
compilation unless the function will actually be used, i.e. when
CONFIG_TEGRA_NAND is defined.

Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, rewrote commit description, moved ifdef around whole function
rather than just body]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Fixed TODO by moving the ifdef around the whole function rather than
  being inside the function body. The call to the function is under the
  same ifdef.
ARM: tegra: fix a typo in the tegra114.dtsi

The reg property for node spi@7000d800 was wrong. Fix it to match the
HW. This change was verified against the Linux kernel.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add/edit headers for Tegra124

These headers define the Tegra124 hardware. Add them to the usual
place.

Add Tegra124 chip ID/SKU ID definitions to common headers.

There's no real HW change on Tegra124 for 90% of the toys, so it might
make sense for a future patch to unify some of the content of these
files in a common location.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Put content directly into files in arch-tegra124/; don't put files there
  that simply include the real files in arch-tegra/.
* Removed unused emc.h, fuse.h.
* Added to arch-tegra/pmc.h rather than creating a new arch-tegra124/pmc.h,
  since some code already includes arch-tegra/pmc.h, and I didn't feel good
  about different code getting different versions of pmc.h.
* Remove error-inducing prototype for board_usb_init().
* Squashed in the other patch which edited arch-tegra/*.h, since they're
  both just adding/editing header files.
* Don't touch Tegra114 SPI header.
* Minor whitespace cleanup.
ARM: tegra: add SPL/AVP (arm720t) CPU files for Tegra124

This provides SPL support for Tegra124 boards - AVP early init, plus
CPU (A15) init/jump to main U-Boot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Convert to Kconfig-style make Makefiles.
* Update AVP/PLLP clock programming to match Tegra114.
* Extracted changes to PLLX programming order into a separate patch.
* Use PLL_LOCK_MASK constant instead of a hard-coded value.
* No need to read-modify-write pmc_pwrgate_toggle or
  crc_clk_cpu_cmplx_clr.
* s/1x4/Tegra124/
* don't mangle (c) header in cpu.c.
* Remove leading space from debug() messages.
* Fix comment re: CPUPWRGOOD_TIMER
* Various code formatting fixes and redundant bracket and comment
  removal.
ARM: tegra: Add CPU (armv7) files for Tegra124

These files are for code that runs on the CPU (A15) on Tegra124 boards.
At this time, there is no A15-specific code here. The warmboot/LP0 files
aren't included as that code hasn't been ported yet.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v3:
* s/tegra30_or_later_adjust_pllp/tegra30_set_up_pllp/ to adjust for a
  change in an earlier patch series.
v2:
* Convert to Kconfig-style make Makefiles.
* s/MASK_BITS_29_28/MASK_BITS_31_28/ to match earlier renaming patch.
* Update AVP/PLLP clock programming to match Tegra114.
* Minor whitespace & comment cleanup.

fixup arch/arm/cpu/tegra124-common/clock.c
ARM: tegra: add common (shared) CPU files

These files are used by both SPL and main U-Boot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Fixed incorrect brace placement in tegra_get_chip_sku(), and allow any
  SKU on Tegra124 just like other SoCs.
* Simplified change to config_cache().
ARM: tegra: add DT files for Tegra124 and Venice2

These are fairly complete, and near-clones of Tegra114 Venice, with an
additional I2C port, and MMC address changes for Tegra124.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Added aliases for SPI devices so they always have the same ID.
* Gave each node a unit address where required.
* Fixed all compatible values to match the Linux kernel.
* s/status = "disable"/status = "disabled"/
* Removed properties and nodes that ara:
 - Non-standard and don't match DTs in U-Boot for earlier Tegra SoCs.
 - Not used or for features that don't yet work.
 - ChromeOS specific.
ARM: tegra: add Venice2 (Tegra124) board

These are the board files for Venice2 (Tegra124), plus the AS3722 PMIC
files. PMIC init will be moved to pmic_common_init later.

This builds/boots on Venice2, SPI/MMC/USB/I2C all work. Audio, display
and WB/LP0 are not supported yet.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Convert to Kconfig-style make Makefiles.
* Updated default environment to enable bootcmd_pxe.
* Removed most functional diffs (i.e. other than SoC name, valid values,
  etc.) between include/configs/tegra1[12]4-common.h.
* Deleted PMIC programming code that was disabled; it can be added later
  if it turns out to be useful.
* Fixed boards.cfg sort order.
* Removed unused define CONFIG_TEGRA_USE_EMC_DRAM_SIZE.
* Minor comment cleanup.
ARM: tegra: fix "bootp" issue for Tegra124 too

Fix the timeout issue after running "bootp" command in U-Boot console.

TXFIFOTHRES bits of TXFILLTUNING register should be set to 0x10 after a
controller reset and before RUN bit is se, (per technical reference
manual.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
LATER: ARM: tegra: add support for more clocks on Tegra114

FIXME: work on this later after Tegra124 support.
FIXME: re-write commit description now it's been split up...

Some Tegra114 peripherals can take up to 8 different clock sources
(parents), including 4 new ones that don't exist on previous chips
(PLLC2/C3/MEM2/SRC2). Expand clock/PLL code/tables to support these
additional bits/sources.

Changes were made to some common code. Testing on Tegra30 and Tegra20
showed no changes in periph clock sources/divisors.

Also, peripheral clock sources that no longer exist on Tegra114 were
removed from the clock_periph_type table (CVE, TVDAC, etc.), and periphs
that are gone or not needed in early init are no longer brought out of
reset/enabled (FUSE, IRAMA/B/C/D, etc.).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v3:
* Undid change to assert on divisor value; the fix was applied to the
  wrong assert. The assert which should have been fixed was within the
  removed unused code.
v2:
- Fixed an assert test for a divisor value (s/b >0, not >=0)
- Remove some unused code
Revert "LATER: ARM: tegra: add support for more clocks on Tegra114"

This reverts commit 6cf0329f447d51e1ad5909d46f79cfd4756a4c93.
LATER: ARM: tegra: dalmore: add PMIC init for various peripherals

FIXME: work on this later after Tegra124 support.

These power rails are currently needed for kernel boot. This will be move
to a PMIC-specific driver (or even better moved to the kernel) at a later
date.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Revert "LATER: ARM: tegra: dalmore: add PMIC init for various peripherals"

This reverts commit 2e5b746676e5360325456184750e979726b4a009.