Add basic AXI4 support to simbus
Core protocol support for most of AXI4

This adds the signals for transaction ids, QoS, locking, caching,
and burst signals. This does not include actual implementations as
that is a matter for the clients.
Fix some AXI4 addressing / Get protocol bit ordering right

AXI4 addresses are BYTE addresses, not word addresses, so get that
(and the AxSIZE fields) correct.

The simbus protocol transmits in big-endian, so get the vectors
ordered correctly.
Add AXI4 support for 8bit read/write.
AXI4 reads/writes 8-64bits wide.

This handles any AXI4-Lite bus width, as long as it is at
least as wide as the word being written. We still require
that the address be aligned.
Install AXI4 slot verilog stub.