new file:   c-code/clock.c
	new file:   verilog-qpfiles/Button_Debounce.v
	new file:   verilog-qpfiles/Clock.qpf
	new file:   verilog-qpfiles/Clock.qsf
	new file:   verilog-qpfiles/Clock.v
	new file:   verilog-qpfiles/Lab3.v
	new file:   verilog-qpfiles/binary_2_BCD.v
	new file:   verilog-qpfiles/clock_SM.v
	new file:   verilog-qpfiles/cpu/CPU_Final_Project.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_btn.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_clock_get.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_clock_set.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_clocks.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu.ocp
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu.sdc
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu_bht_ram.mif
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu_dc_tag_ram.mif
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu_ic_tag_ram.mif
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu_jtag_debug_module_sysclk.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu_jtag_debug_module_tck.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu_jtag_debug_module_wrapper.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu_mult_cell.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu_oci_test_bench.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu_ociram_default_contents.mif
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu_rf_ram_a.mif
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu_rf_ram_b.mif
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_cpu_test_bench.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_irq_mapper.sv
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_jtag_uart.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_lcd_16207_0.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_ledg.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_ledr.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_mm_interconnect_0.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_mm_interconnect_0_addr_router.sv
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_mm_interconnect_0_addr_router_001.sv
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_mm_interconnect_0_cmd_xbar_demux.sv
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_mm_interconnect_0_cmd_xbar_demux_001.sv
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_mm_interconnect_0_cmd_xbar_mux.sv
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_mm_interconnect_0_cmd_xbar_mux_002.sv
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_mm_interconnect_0_id_router.sv
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_mm_interconnect_0_id_router_002.sv
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_mm_interconnect_0_rsp_xbar_demux.sv
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_mm_interconnect_0_rsp_xbar_demux_002.sv
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_mm_interconnect_0_rsp_xbar_mux.sv
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_mm_interconnect_0_rsp_xbar_mux_001.sv
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_sram.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_switch.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_sysid.v
	new file:   verilog-qpfiles/cpu/submodules/CPU_Final_Project_timer_0.v
	new file:   verilog-qpfiles/cpu/submodules/altera_avalon_sc_fifo.v
	new file:   verilog-qpfiles/cpu/submodules/altera_avalon_st_pipeline_base.v
	new file:   verilog-qpfiles/cpu/submodules/altera_merlin_arbitrator.sv
	new file:   verilog-qpfiles/cpu/submodules/altera_merlin_burst_uncompressor.sv
	new file:   verilog-qpfiles/cpu/submodules/altera_merlin_master_agent.sv
	new file:   verilog-qpfiles/cpu/submodules/altera_merlin_master_translator.sv
	new file:   verilog-qpfiles/cpu/submodules/altera_merlin_reorder_memory.sv
	new file:   verilog-qpfiles/cpu/submodules/altera_merlin_slave_agent.sv
	new file:   verilog-qpfiles/cpu/submodules/altera_merlin_slave_translator.sv
	new file:   verilog-qpfiles/cpu/submodules/altera_merlin_traffic_limiter.sv
	new file:   verilog-qpfiles/cpu/submodules/altera_reset_controller.sdc
	new file:   verilog-qpfiles/cpu/submodules/altera_reset_controller.v
	new file:   verilog-qpfiles/cpu/submodules/altera_reset_synchronizer.v
Merge branch 'master' of https://github.com/jcallow/Digital-Clock-FP