clk: sunxi: Add A23 APB0 divider clock support

The A23 has an almost identical PRCM clock tree. The difference in
the APB0 clock is the smallest divisor is 1, instead of 2.

This patch adds a separate sun8i-a23-apb0-clk driver to support it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
clk: sunxi: Fix gate indexing for sun6i-a31-apb0-gates

sun6i-a31-apb0-gates supports using clock-indices for holes between
individual gates. However, the driver passes the number of gates
registered in clk_data->clk_num, which of_clk_src_onecell_get uses
to recognize the range of valid indices a consumer can use.

This patch makes the driver pass the maximum gate index + 1, so
of_clk_src_onecell_get does not complain about indices greater
than gates registered.

This was tested on the A23 SoC, which has a similar APB0 clock,
but has holes for gates to removed IP blocks.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clk: sunxi: Add A23 specific compatible to sun6i-a31-apb0-gates-clk

The sun6i-a31-apb0-gates-clk driver is generic in that it supports
the "clock-indicies" DT property with "clock-output-names" to list
the valid clock gate bits.

However this might lead one to assume that the clock in the A23 is
the same as the A31. To make it clear, we add a new compatible for
the A23, "allwinner,sun8i-a23-apb0-gates-clk".

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
mfd: sun6i-prcm: Add support for Allwinner A23 PRCM

The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC.
The differences are the AR100 clock can no longer be modified,
the APB0 clock has different divisors, and some clock gates are
gone.

This patch adds a compatible with a modified subdevice list for
the A23.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
serial: 8250_dw: Add optional reset control support

The Allwinner A31 and A23 SoCs have a reset controller
maintaining the UART in reset by default.

This patch adds optional reset support to the driver.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
serial: 8250_dw: Add support for deferred probing

The 8250_dw driver fails to probe if the specified clock isn't
registered at probe time. Even if a clock frequency is given,
the required clock might be gated because it wasn't properly
enabled.

This happened to me when the device is registered through DT,
and the clock was part of an MFD, the PRCM found on A31 and A23
SoCs. Unlike core clocks that are registered with OF_CLK_DECLARE,
which happen almost immediately after the kernel starts, the
clocks are registered as sub-devices of the PRCM MFD platform
device. Even though devices are registered in the order they are
found in the DT, the drivers are registered in a different,
arbitrary order. It is possible that the 8250_dw driver is
registered, and thus associated with the device and probed, before
the clock driver is registered and probed.

8250_dw then reports unable to get the clock, and fails. Without
a working console, the kernel panics.

This patch adds support for deferred probe handling for the clock
and reset controller.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: sunxi: select MFD_SUN6I_PRCM when sun8i arch support is enabled

Select the MFD_SUN6I_PRCM option when sun8i arch is enabled in order to
get the PRCM (Power/Reset/Clock Management) related drivers compiled.

Also select ARCH_HAS_RESET_CONTROLLER and RESET_CONTROLLER to make sure
the reset controller drivers are compiled.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: sun8i: Add PRCM clock and reset controller nodes to the DTSI

With sun8i PRCM support available, we can add the PRCM clock and
reset controller nodes to the DTSI. Also update R_UART's clock
phandle and add it's reset control phandle.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ARM: sun8i: Add reset controller nodes to the DTSI

The A23 has the same MMIO reset controllers matching the clocks gates,
just like in the A31. This patch adds the reset controller nodes and
the reset control phandles for the peripherals needing them to the
DTSI.

Unlike the sun6i DTSI, this patch uses sun6i-a31-clock-reset for
ahb1_rst. sun6i-a31-ahb-reset is for early init, and requires some
additions to the machine code. It is used to support the hstimer.
However the hstimer on sun8i only has 1 timer, which is somewhat
useless. Support for it will probably not be added. Hence the
decision to use sun6i-a31-clock-reset here to avoid the changes to
sun8i machine code.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>