Change fe_frombytes and fe_tobytes to modules

- Change fe_frombytes and fe_tobytes to modules
- Update modules that use fe_frombytes and fe_tobytes
- Update testbed codes
Tweak ignore
Merge remote-tracking branch 'origin/verilog'
Bump clock
Version 1.2.9, nearly closes timing at 100 Mhz
Version 1.2.9 release