fixup constrain
tcg-mips: Split large ldst offsets

Use this to reduce goto_tb by one insn.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Move softmmu slow path out of line

At the same time, tidy up the call helpers, avoiding a memory reference.
Split out several subroutines.  Use TCGMemOp constants.  Make endianness
selectable at runtime.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Convert to new qemu_l/st helpers

In addition, fill delay slots calling the helpers and tail
call to the store helpers.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Convert to new_ldst

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Rearrange register allocation

Use FP (also known as S8) as a normal call-saved register.

Include T0 in the allocation order and call-clobbered list
even though it's currently used as a TCG temporary.

Put the argument registers at the end of the allocation order.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Introduce TCG_TMP0, TCG_TMP1

Use these instead of hard-coding the registers to use for temporaries.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Use T9 for TCG_TMP1

T0 is an argument register for the n32 and n64 abis.  T9 is the call
address register for the abis, and is more directly under the control
of the backend.

Signed-off-by: Richard Henderson <rth@twiddle.net>
fixup intro tmp0
tcg-mips: Use EXT for AND on mips32r2

At the same time, tidy deposit by introducing tcg_out_opc_bf.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Name the opcode enumeration

And use it in the opcode emission functions.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Fix subtract immediate range

Since we must use ADDUI, we would generate incorrect code for -32768.
Leaving off subtract of +32768 makes things easier for a follow-on patch.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Hoist args loads

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Improve add2/sub2

Reduce insn count from 5 to either 3 or 4.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Commonize opcode implementations

Most opcodes fall in to one of a couple of patterns.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Simplify setcond

Use a table to fold comparisons to less-than.
Also, move the function up in the file for futher simplifications.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Simplify brcond

Use the same table to fold comparisons as with setcond.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Simplify setcond2

Using tcg_unsigned_cond and tcg_high_cond.
Also, move the function up in the file for future cleanups.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Improve setcond eq/ne vs zeros

The original code results in one too many insns per zero
present in the input.  And since comparing 64-bit numbers
vs zero is common...

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-mips: Simplify brcond2

Emitting a single branch instead of (up to) 3, using setcond2
to generate the composite compare.

Signed-off-by: Richard Henderson <rth@twiddle.net>