For Exynos4 platforms, re-implement PoP detection so we can detect 1Gb
systems.
Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init the sdcache and sdcache info.
Add hook to set L2 cache to write-through
Use correct library path for -m32 on sparc64.
Implement sscom interrupt masking and acknowledgement routines
Add a vacookie to busdma_segment, for potential help with bus_dmamem_map()
be even more explicit about handling only bus 0
add necessary -I for /dev/pci* creation
* make it possible for rumpcomp_pci_intr_establish() to know which
  device it's establishing the interrupt for
* make it possible to implement bus_dmamem_map() properly
fix typo
build hypercalls if RUMP_PCI_USER is defined
Checking in cosmetic changes -- no functional change.
(Suggestions made by Taylor Campbell)
There's no need for this NULL-check.
Fix a deadlock where one thread exits, enters fstrans_lwp_dtor()
and wants fstrans_lock.  This thread holds the proc_lock.
Another thread holds fstrans_lock and runs pserialize_perform().
As the first thread holds the proc_lock, timeouts are blocked and
the second thread blocks forever in kpause().

Change fstrans_lwp_dtor() to invalidate, but not free its info
structs.  No need to take fstrans_lock.

Change fstrans_get_lwp_info() to reuse invalidated info before
trying to allocate a new one.
Append to CPPFLAGS.${src}, don't overwrite it.
print chip revision on attach
cpu0 at mainbus0: mid 8: RT620/625 @ 125000  MHz, on-chip FPU
unfortunately that's too good to be true, so print frequency in MHz when we
say it's in MHz