Fix in InlineSpiller to make the rematerilization loop also consider
implicit uses of the whole register when a sub register is defined.

Now the same iterator is used in the rematerilization loop as in the
spill loop later.

Patch provided by Mikael Holmen.

This fix was proposed and reviewed by Quentin Colombet,
http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/076135.html.

Unfortunately, this error in the rematerilization code has only been
seen in a large test case for an out-of-tree target, and is probably
hard to reproduce on an in-tree target. Therefore, no testcase is
provided.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216873 91177308-0d34-0410-b5e6-96231b3b80d8
Thumb2 M-class MSR instruction support changes

This patch implements a few changes related to the Thumb2 M-class MSR instruction:
 * better handling of unpredictable encodings,
 * recognition of the _g and _nzcvqg variants by the asm parser only if the DSP
   extension is available, preferred output of MSR APSR moves with the _<bits>
   suffix for v7-M.

Patch by Petr Pavlu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216874 91177308-0d34-0410-b5e6-96231b3b80d8
[asan-assembly-instrumentation] Prologue and epilogue are moved out from InstrumentMemOperand().

Reviewers: eugenis

Subscribers: llvm-commits

Differential revision: http://reviews.llvm.org/D4923

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216879 91177308-0d34-0410-b5e6-96231b3b80d8
ARM] Add Thumb-2 code size optimization regression test for BIC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216880 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM] Add Thumb-2 code size optimization regression test for EOR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216881 91177308-0d34-0410-b5e6-96231b3b80d8