target-arm: A64: Add SIMD ld/st multiple

This adds support support for the SIMD load/store
multiple category of instructions.

This also brings in a couple of helper functions for manipulating
sections of the SIMD registers:

  * do_vec_get - fetch value from a slice of a vector register
  * do_vec_set - set a slice of a vector register

which use vec_reg_offset for consistent processing of offsets in an
endian aware manner. There are also additional helpers:

  * do_vec_ld - load value into SIMD
  * do_vec_st - store value from SIMD

which load or store a slice of a vector register to memory.
These don't zero extend like the fp variants.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add SIMD ld/st single

Implement the SIMD ld/st single structure instructions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add decode skeleton for SIMD data processing insns

Add decode skeleton and function placeholders for all the SIMD data
processing instructions. Due to the complexity of this part of the
table the normal extract and switch approach gets very messy very
quickly, so we use a simple data-driven pattern-and-mask approach.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add SIMD EXT

Add support for the SIMD EXT instruction (the only one in its
group, C3.6.1).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add SIMD TBL/TBLX

Add support for the SIMD TBL/TBLX instructions (group C3.6.2).

Signed-off-by: Michael Matz <matz@suse.de>
[PMM: rewritten to do more of the decode in translate-a64.c,
 and to do only one 64 bit pass at a time in the helper]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add SIMD ZIP/UZP/TRN

Add support for the SIMD ZIP/UZIP/TRN instruction group
(C3.6.3).

Signed-off-by: Michael Matz <matz@suse.de>
[PMM: use new do_vec_get/set etc functions and generally update to new
 codebase standards; refactor to pull per-element loop outside switch]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add SIMD across-lanes instructions

Add support for the SIMD "across lanes" instruction group (C3.6.4).

Signed-off-by: Michael Matz <matz@suse.de>
[PMM: Updated to current codebase, added fp min/max ops,
 added unallocated encoding checks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add SIMD copy operations

This adds support for the all the AdvSIMD vector copy operations
(ARM ARM 3.6.5).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add SIMD modified immediate group

This patch adds support for the AdvSIMD modified immediate group
(C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic).

Signed-off-by: Alexander Graf <agraf@suse.de>
[AJB: new decode struct, minor bug fixes, optimisation]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add SIMD scalar copy instructions

Add support for the SIMD scalar copy instruction group (C3.6.7),
which consists of the single instruction DUP (element, scalar).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
dataplane: fix shadowed return value

Propagate the error return value from get_indirect().

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
target-arm: A64: Add SIMD three-different multiply accumulate insns

Add support for the multiply-accumulate instructions from the
SIMD three-different instructions group (C3.6.15):
 * skeleton decode of unallocated encodings and split of
   the group into its three sub-parts
 * framework for handling the 64x64->128 widening subpart
 * implementation of the multiply-accumulate instructions
   SMLAL, SMLAL2, UMLAL, UMLAL2, SMLSL, SMLSL2, UMLSL, UMLSL2,
   UMULL, UMULL2, SMULL, SMULL2

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Add SIMD three-different ABDL instructions

Implement the absolute-difference instructions in the SIMD
three-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL,
SABDL2, UABDL, UABDL2.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops

Implement the add, sub and compare ops from the SIMD "scalar three same"
group.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Support logic ops from SIMD 3 same group

Add support for the logical operations (ORR, AND, BIC, ORN, EOR, BSL,
BIT and BIF) from the SIMD 3 register same group (C3.6.16).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v3 (ajb)
   - port to new structure/API
   - hoist do_vec_get to common code for B* ops
   - no need to test opcode, will always be correct
   - rename to handle_simd_three_same_logic

v4 (ajb):
   - new names for vector accessor

v5 (pmm):
 * cleaned up commit message
 * use loop through 2 passes rather than repetitive if_q code
target-arm: A64: Add simple 64 bit insns from scalar 2-reg misc

Implement the simple 64 bit integer operations from the SIMD
scalar 2-register misc group (C3.6.12): the comparisons against
zero, plus ABS and NEG.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: A64: Add SIMD shift by immediate

This implements a subset of the AdvSIMD shift operations (namely all the
none saturating or narrowing ones). The rounding operations need to take
special care to correctly reflect the result of adding rounding bits on
high bits as the intermediates do not truncate.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v3 (ajb):
   - port to new framework/APIs
   - ensure we correctly sign extend when needed
   - catch all ReservedValues
   - fix unallocated/unsupported ambiguities
   - ensure round_const properly cast to 64bit
   - use 128bit arithmetic to properly handle rounding
   - fix sizes for sshll2/sxtl widening insns
   - catch special cases of shift of #64 (tcg banckend NOP)
   - add SLI

v4 (ajb)
   - new names for vector helper functions

v5 (ajb)
   - clean up wording of comments
   - rm stray trace operation
   - improve codegen for extended case
   - use built in extension helper
   - don't bother calculating ebytes (we have esize)
   - rm pointless check for !immh
   - push calculations as far down a possible
   - only calculate lshift for size == 3
   - remove double shift, either it's zeros or sign bit
translate-a64.c: add a debug helper trace macro

This just makes it easier to drop TRACE_DECODE statements all over the
place instead of fprintfs.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v2 (ajb)
   - checkpatch.pl fixes
rm unused field
scripts/qemu-binfmt-conf.sh: re-factor and clean-up

I was looking to set-up for development but found the script made some
hard-coded assumptions. It doesn't seem the script is used by the
distros but if it had a little more love maybe it would be ;-)

* Add usage() instructions
* Move all registering to a single function
* Check for existence of executable qemu before registering
* Add -d (devel) mode for subscribing in-src tree binaries
* error handling when setting binfmt fails
* add support for aarch64