regulator: mc13892: Fix checkpatch issue

Fix the following checkpatch warnings.

  WARNING: Avoid unnecessary line continuations
  WARNING: line over 80 characters

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
OMAPDSS: fix omap2 dss fck handling

The driver considers OMAP2 DSS's functional clock as a fixed clock.
However, it can be changed, but the possible dividers are not continuous
which is why it was just handled as a fixed clock.

As a partial fix, this patch changes the code to handle the continous
part of the dividers, from 1 to 6. This let's us handle the OMAP2 fck
the same way as fcks on other OMAPs.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
OMAPDSS: remove struct dss_clock_info

Remove struct dss_clock_info, as it is not usable in a case where DSS
fclk comes from a dedicated PLL. Instead, just use the fclk rate in
place of dss_clock_info, as that is all that's needed.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
OMAPDSS: simplify dss clk dump

Simplify dss_dump_clocks() so that it doesn't make any presumptions
about the DSS fclks nature.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
OMAPDSS: rename parent clk variables

Rename the variables related to DSS fclk's parent: "clk_name" and
"dpll4_m4_ck", to "parent_clk_name" and "parent_clk", which much better
tell what they mean.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
OMAPDSS: cleanup fck parent handling

The dss parent_clk_name currently points to a clock node which we use to
change the fclk rate. Now that we have CLK_SET_RATE_PARENT properly set,
we can set the rate directly to the fclk node.

However, we still need to calculate the possible clock rates. For this,
we need the rate of the parent of the current parent_clk.

To simplify the code, this patch changes the parent_clk_name to point to
the above mentioned parent, so that we can get the rate directly.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
OMAPDSS: pass pck to dss fck clock calc

We need the required pixel clock rate when calculating the dss fclk on
SoCs that have a dedicated DSS PLL.

This patch changes the code to pass the pck to the calc functions. The
pck rate is taken into use in the next patch.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
OMAPDSS: add dedicated fck PLL support

This patch adds support for SoCs that have a dedicated DSS PLL used for
DSS function clock.

If there is no dss parent clock defined, it is presumed that the
functionl clock rate can be set (almost) freely. The code calculates the
highest allowed fck rate, which when divided with some integer gives the
required pck.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
drm/rcar-du: fix return value check in rcar_du_lvdsenc_get_resources()

In case of error, the function devm_ioremap_resource() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check should be
replaced with IS_ERR(). Also remove the dev_err call to avoid redundant
error message.

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
drm/rcar-du: Don't cast crtc to rcrtc twice in the same function

Reuse the previously cast variable instead.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
drm/rcar-du: Update plane pitch in .mode_set_base() operation

When setting a new frame buffer with the mode set base operation the
pitch value might change. Set the hardware plane pitch register at the
same time as the plane base address in the rcar_du_plane_update_base()
function to make sure the pitch value always matches the frame buffer.

Cc: stable@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
drm/rcar-du: Split features and quirks

128-byte pitch alignement is not a hardware feature, it's a hardware
bug. Split it from the features field into a new quirks field. New
quirks will be added to support the R8A7791 SoC.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
drm/rcar-du: Add LVDS_LANES quirk

LVDS lanes 1 and 3 are switched in ES1 hardware (R8A7790). The problem
has been fixed in newer revisions, add a quirk to make the workaround
selectable.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
drm/rcar-du: Add support for the r8a7791 DU

The r8a7791 DU is a stripped-down version of the r8a7790 DU with two
CRTCs and a single LVDS output.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
ARM: bcm_defconfig: CONFIG_OABI_COMPAT default off

Now that CONFIG_OABI_COMPAT is off by default, remove the explicit
disabling of this feature.

Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
ARM: bcm_defconfig: Do not expect appended DTB

The bootloaders used with Broadcom mobile SoCs are capable of handling
a device tree separately from the zImage so there is no need for this
option to be enabled.

Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
ARM: bcm_defconfig: Unset CONFIG_CRYPTO_ANSI_CPRNG

Do not build the Pseudo Random Number Generation for Cryptographic
modules since it is not currently being used for this platform.

Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
ARM: ux500: delete U8540 UART auxdata

The other Ux500's does not need this anymore, and the U8540
certainly is no different.

Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
ARM: ux500: Refactor common DT configs for sdi[n] devices

Remove duplicated configurations and move specific details into
each corresponding dtsi file for the href versions.

Cc: Lee Jones <lee.jones@linaro.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
ARM: ux500: Configure regulator for I/O voltage for SD-card slot

To be able to enable SDR12|25 for SD-cards, we needed to fixup the
configuration in DT of the gpio regulator, which handles the signal
voltage level. Some configuration were missing and some were wrong.

Cc: Lee Jones <lee.jones@linaro.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>