freedreno/ir3: detect scheduler fail

There are some cases where the scheduler can get itself into impossible
situations, by scheduling the wrong write to pred or addr register
first.  (Ie. it could end up being unable to schedule any instruction if
some instruction which depends on the current addr/reg value also
depends on another addr/reg value.)

To solve this we'd need to be able to insert extra mov instructions
(which would also help when register assignment gets into impossible
situations).  To do that, we'd need to move the nop padding from sched
into legalize.

But to start with, just detect when we get into an impossible situation
and bail, rather than sitting forever in an infinite loop.  This way it
will at least fall back to the old compiler, which might even work if
you are lucky.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/ir3: add TXB

Signed-off-by: Rob Clark <robclark@freedesktop.org>
freedreno/ir3: fix potential null ptr deref

Fix potential segfault in debug code.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
st/hgl: Move st_manager create/destroy into hgl state_tracker
st/hgl: Move st_visual create/destroy into hgl state_tracker
ilo: replace cmd by dw0 in GPE

With e3c251071b0c9396c3ec76d1cf943c60ae297281, the magic values are gone.  We
no longer need "cmd" to hide them.  Replace it by dw0.
ilo: fix bound check for 3DSTATE_URB_VS

Fix max/min entries on GEN7.5 GT2/GT3.
ilo: set INTEL_RELOC_GGTT only on GEN6

We asked MI commands to use GGTT only on GEN6.
i965: Use unreachable() to silence warning.

brw_meta_fast_clear.c:211:17: warning: 'x_scaledown' may be used
uninitialized in this function [-Wmaybe-uninitialized]
    unsigned int x_scaledown, y_scaledown;

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/vec4: Update register coalescing test.

In commit 04895f5c I added support for reswizzling writemasks. This test
was checking that we didn't support this.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82881
i965: Add 2x MSAA support to Broadwell fast clear code.

According to the cited documentation section (but in the newer docs),
x_scaledown is the same for 2x and 4x MSAA.

+47 piglits.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83081
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
tgsi/ureg: add ureg_UARL shortcut
mesa/gallium: API settings / rasterization rules

Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
radeon/softpipe/llvmpipe/svga/i915/ilo/freedreno/nv30: use API settings / rasterization rules

v2: compilation fixes by David Heidelberger <david.heidelberger@ixit.cz>
v3: compilation fix by Thermionix <bond711@gmail.com>

Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
gallium/nvc0: improve code readability

Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
nv50/nvc0: use API settings / rasterization rules

Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
nv50,nvc0: handle TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
nv50,nvc0: handle NULL vertex elements without fallback
nv50/ir/tgsi: implement TGSI_OPCODE_NRM,DP2A

Used by d3d9 st.
hack/nv50: don't emit buffer for skipped vertex elements

Grr, should forbid that and insert dummy elements in nine.